Transceivers; Figure 7-8: Clock Management - Multiple Core Instances, Virtex-5 Rocketio Gtx - Xilinx LogiCORE 1000BASE-X User Manual

Clock Sharing Across Multiple Cores with RocketIO
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008

Figure 7-8: Clock Management - Multiple Core Instances, Virtex-5 RocketIO GTX

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DCM
BUFG
CLKIN CLK0
BUFG
FB
CLKDV
userclk (62.5MHz) userclk2 (125MHz)
component_name_block
(Block Level)
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
component_name_block
(Block Level)
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
Transceivers for 1000BASE-X
R
IBUFGDS
brefclkp
IPAD
IPAD
clkin
brefclkn
(125MHz)
rocketio_wrapper_gtp
rocketio_wrapper_gtp_tile
Virtex-5
GTP
RocketIO
(0)
REFCLKOUT
TXUSRCLK0
TXUSRCLK20
RXUSRCLK0
RXUSRCLK20
CLKIN
Virtex-5
GTP
RocketIO
(1)
TXUSRCLK1
TXUSRCLK21
RXUSRCLK1
RXUSRCLK21
rocketio_wrapper_gtp
rocketio_wrapper_gtp_tile
Virtex-5
GTP
RocketIO
(0)
NC REFCLKOUT
TXUSRCLK0
TXUSRCLK20
RXUSRCLK0
RXUSRCLK20
CLKIN
Virtex-5
GTP
RocketIO
(1)
TXUSRCLK1
TXUSRCLK21
RXUSRCLK1
RXUSRCLK21
93