Virtex-5 Lxt And Sxt Devices - Xilinx LogiCORE 1000BASE-X User Manual

RocketIO Transceiver Logic

Virtex-5 LXT and SXT Devices

The core is designed to integrate with the Virtex-5 RocketIO GTP transceiver.
illustrates the connections and logic required between the core and the GTP transceiver—
the signal names and logic in the figure precisely match those delivered with the example
design when a GTP transceiver is used.
Note:
port differences between the Virtex-II Pro and Virtex-5 GTP transceiver.
A GTP tile consists of a pair of transceivers. For this reason, the GTP transceiver wrapper
delivered with the core always contains two GTP instantiations, even if only a single GTP
transceiver tile is in use.
The 125 MHz differential reference clock is routed directly to the GTP transceiver. The GTP
transceiver is configured to output a version of this clock on the REFCLKOUT port and after
placement onto global clock routing, can be used by all core logic. This clock is input back
into the GTP transceiver on the user interface clock ports rxusrclk, rxusrclk2,
txusrclk, and txusrclk2.
See also
Virtex-5 RocketIO GTP Wizard
The two wrapper files immediately around the GTP transceiver pair,
rocketio_wrapper_gtp_tile and rocketio_wrapper_gtp (see
generated from the RocketIO GTP Wizard. These files apply all the gigabit Ethernet
attributes. Consequently, these files can be regenerated by customers and therefore be
easily targeted at ES or Production silicon. Note that this core targets production silicon.
The CORE Generator log file (XCO file) which was created when the RocketIO GTP Wizard
project was generated is available in the following location:
This file can be used as an input to the CORE Generator to regenerate the RocketIO
wrapper files. The XCO file itself contains a list of all of the GTP Wizard attributes which
were used. For further information, please refer to the Virtex-5 RocketIO GTP Wizard Getting
Started Guide (UG188) and the CORE Generator Guide, at
www.xilinx.com/support/software_manuals.htm
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
A small logic shim (included in the block-level wrapper) is required to convert between the
Figure 7-3
"Virtex-5 RocketIO GTP Transceivers for 1000BASE-X Constraints," page
<project_directory>/<component_name>/example_design/transceiver/
rocketio_wrapper_gtp.xco
www.xilinx.com
illustrates a single GTP transceiver tile.
R
Figure 7-3
166.
Figure 7-3), are
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