Xilinx LogiCORE 1000BASE-X User Manual page 47

Design Overview
1000BASE-X Standard with TBI Example Design
Figure 4-2
the example is split between two hierarchical layers. The block level is designed so that it
can be instantiated directly into customer designs and performs the following functions:
•
•
The top level of the example design creates a specific example that can be simulated,
synthesized, implemented, and if required, placed on a suitable board and demonstrated
in hardware. The top level of the example design performs the following functions:
•
•
•
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
illustrates the example design in 1000BASE-X mode using a TBI. As illustrated,
Instantiates the core from HDL
Connects the physical-side interface of the core to device IOBs, creating an external
TBI. See Chapter 6, "The Ten-Bit Interface."
Instantiates the block level from HDL
Derives the clock management logic for the core
Implements an external GMII
component_name_example_design
GMII
IOBs
In
Connect to
Client MAC
IOBs
Out
Clock
Management
Logic
Figure 4-2: Example Design 1000BASE-X Standard Using TBI
www.xilinx.com
component_name_block
Tx
Elastic
Buffer
Ethernet
1000BASE-X
PCS/PMA
Core
TBI
IOBs
Out
TBI
(Connect to
SERDES)
IOBs
In
(DDR)
R
47