Chapter 2: Core Architecture; System Overview; Ethernet 1000Base-X Pcs/Pma Or Sgmii Using A Rocketio Transceiver - Xilinx LogiCORE 1000BASE-X User Manual

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Core Architecture
This chapter describes the architecture of the Ethernet 1000BASE-X PCS/PMA or SGMII
core, including all interfaces and major functional blocks.

System Overview

Ethernet 1000BASE-X PCS/PMA or SGMII Using A RocketIO Transceiver

The Ethernet 1000BASE-X PCS/PMA or SGMII core provides the functionality to
implement the 1000BASE-X PCS and PMA sub-layers or used to provide a GMII to SGMII
bridge when used with a RocketIO transceiver. RocketIO transceivers are defined in the
following way:
•
•
The core interfaces to a RocketIO transceiver, providing some of the PCS layer
functionality such as 8B/10B encoding/decoding, the PMA SERDES, and clock recovery.
Figure 2-1
functional blocks of the core.
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
For Virtex-II Pro and Virtex-4 devices, RocketIO Multi-Gigabit Transceivers (MGT)
For Virtex-5 LXT and SXT FPGAs, RocketIO GTP transceivers; Virtex-5 FXT FPGA,
RocketIO GTX transceiver
illustrates the remaining PCS sublayer functionality, and also shows the major
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Chapter 2
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