Xilinx LogiCORE 1000BASE-X User Manual page 62

R
Virtex-II Pro and Virtex-II Devices
Figure 5-14
device. The signal names and logic shown on the figure exactly match those delivered with
the example design.
Figure 5-14
presenting them to the FPGA fabric. This logic achieves the required setup and hold times.
IBUFG
gmii_tx_clk
IPAD
IBUF
gmii_txd[0]
IPAD
IBUF
gmii_tx_en
IPAD
IBUF
gmii_tx_er
IPAD
62
illustrates how to create an external GMII transmitter in a Virtex-II family
shows that the input transmitter signals are registered in device IOBs before
IOB LOGIC
gmii_tx_clk_ibufg
gmii_txd_ibuf[0] gmii_txd_int[0]
D Q
gmii_tx_en_ibuf gmii_tx_en_int
D Q
gmii_tx_er_int
gmii_tx_er_ibuf
D Q
Figure 5-14: GMII Transmitter Logic
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Chapter 5: Using the Client-side GMII Data Path
BUFG
gmii_tx_clk_bufg
userclk2 (if RocketIO is used)
gtx_clk (if TBI is used)
Transmitter
Elastic
Buffer
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
Ethernet 1000BASE-X
PCS/PMA
or SGMII LogiCORE
gmii_txd[0]
gmii_tx_en
gmii_tx_er
UG155 March 24, 2008