Figure 7-2: 1000Base-X Connection To Virtex-4 Mgt - Xilinx LogiCORE 1000BASE-X User Manual

R
82
userclk2 (125MHz)
component_name_block
(Block Level from
example design)
Ethernet 1000BASE-X
PCS/PMA or SGMII
LogiCORE
userclk
userclk2
rxchariscomma
rxbufstatus[1:0]
rxcharisk
rxclkcorcnt[2:0]
rxdata[7:0]
rxrundisp
rxdisperr
powerdown
txchardispmode
txchardispval
txcharisk
txdata[7:0]
enablealign
BUFG
dclk
signal_detect

Figure 7-2: 1000BASE-X Connection to Virtex-4 MGT

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Chapter 7: 1000BASE-X with RocketIO Transceivers
brefclkp
(250 MHz)
IPAD
IPAD
brefclkn
(250 MHz)
BUFG
'0'
'0'
LOGIC
SHIM
'1'
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
Virtex-4
GT11CLK_MGT
MGTCLKP
MGTCLKN
synclk1
SYNCLK1OUT
Virtex-4
GT11
RocketIO
(used)
REFCLK1
TXOUTCLK1
TXUSRCLK
TXUSRCLK2
RXUSRCLK
RXUSRCLK2
RXCHARISCOMMA
RXBUFERR
RXCHARISK
RXSTATUS[5:0]
RXDATA[7:0]
RXRUNDISP
RXDISPERR
POWERDOWN
TXCHARDISPMODE
TXCHARDISPVAL
TXCHARISK
TXDATA[7:0]
ENPCOMMAALIGN
ENMCOMMAALIGN
DCLK
Cal Block v1.4.1
DCLK
RX_SIGNAL_DETECT
TX_SIGNAL_DETECT
UG155 March 24, 2008