Figure 7-7: Clock Management - Multiple Core Instances, Virtex-5 Rocketio Gtp - Xilinx LogiCORE 1000BASE-X User Manual

Clock Sharing Across Multiple Cores with RocketIO
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008

Figure 7-7: Clock Management - Multiple Core Instances, Virtex-5 RocketIO GTP

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component_name_block
(Block Level)
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk2
userclk
(125 MHz)
userclk2
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
component_name_block
(Block Level)
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
Transceivers for 1000BASE-X
brefclkp IBUFGDS
IPAD
IPAD
BUFG
brefclkn
rocketio_wrapper_gtp
rocketio_wrapper_gtp_tile
Virtex-5
GTP
RocketIO
(0)
REFCLKOUT
TXUSRCLK0
TXUSRCLK20
RXUSRCLK0
RXUSRCLK20
CLKIN
Virtex-5
GTP
RocketIO
(1)
TXUSRCLK1
TXUSRCLK21
RXUSRCLK1
RXUSRCLK21
rocketio_wrapper_gtp
rocketio_wrapper_gtp_tile
Virtex-5
GTP
RocketIO
(0)
NC REFCLKOUT
TXUSRCLK0
TXUSRCLK20
RXUSRCLK0
RXUSRCLK20
CLKIN
Virtex-5
GTP
RocketIO
(1)
TXUSRCLK1
TXUSRCLK21
RXUSRCLK1
RXUSRCLK21
R
clkin
(125MHz)
91