Xilinx LogiCORE 1000BASE-X User Manual page 137

Management Registers
Table 9-19: SGMII Control (Register 0) (Continued)
Register 1: SGMII Status
Table 9-20: SGMII Status (Register 1)
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Bit(s) Name
0.5 Unidirectiona Enable transmit regardless of
l Enable whether a valid link has been
established
0.4:0 Reserved Always return 0s , writes ignored
15 14 13 12 11 10
Reg 1
Bit(s) Name
1.15 100BASE-T4
1.14 100BASE-X Full
Duplex
1.13 100BASE-X Half
Duplex
1.12 10 Mbps Full Duplex
1.11 10 Mbps Half Duplex
1.10 100BASE-T2 Full
Duplex
1.9 100BASE-T2 Half
Duplex
1.8 Extended Status
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Description
MDIO Register 1: SGMII Status
9 8 7
Description
Always returns a '0' for this bit because
100BASE-T4 is not supported
Always returns a '0' for this bit because
100BASE-X Full Duplex is not supported
Always returns a '0' for this bit because
100BASE-X Half Duplex is not supported
Always returns a '0' for this bit because 10
Mbps Full Duplex is not supported
Always returns a '0' for this bit because 10
Mbps Half Duplex is not supported
Always returns a '0' for this bit because
100BASE-T2 Full Duplex is not supported
Always returns a '0' for this bit because
100BASE-T2 Half Duplex is not
supported
Always returns a '1' for this bit to indicate
the presence of the Extended Register
(Register 15)
Attributes
read/ write
returns 0s
6 5 4 3 2 1 0
Attributes
returns 0
returns 0
returns 0
returns 0
returns 0
returns 0
returns 0
returns 1
R
Default
Value
0
00000
Default
Value
0
0
0
0
0
0
0
1
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