Gmii Reception - Xilinx LogiCORE 1000BASE-X User Manual

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10 Megabit per Second Frame Transmission
The operation of the core remains unchanged. It is the responsibility of the client logic (for
example, an Ethernet MAC), to enter data at the correct rate. When operating at a speed of
10 Mbps, every byte of the MAC frame (from destination address to the frame check
sequence field, inclusive) should each be repeated for 100 clock periods to achieve the
desired bit rate. It is also the responsibility of the client logic to ensure that the interframe
gap period is legal for the current speed of operation.

GMII Reception

1 Gigabit per Second Frame Reception
The timing of normal inbound frame transfer is illustrated in
the operation of the receiver GMII signals remains identical to that described in
"Designing with the Client-side GMII for the 1000BASE-X Standard" in Chapter
100 Megabit per Second Frame Reception
The operation of the core remains unchanged. When operating at a speed of 100 Mbps,
every byte of the MAC frame (from destination address to the frame check sequence field,
inclusive) is repeated for 10 clock periods to achieve the desired bit rate. See
is the responsibility of the client logic, for example an Ethernet MAC, to sample this data
correctly.
60
userclk2
gmii_rxd[7:0] preamble
gmii_rx_dv
gmii_rx_er
Figure 5-12: GMII Frame Reception at 1 Gbps
userclk2
gmii_rxd[7:0]
preamble
gmii_rx_dv
gmii_rx_er
Figure 5-13: GMII Data Reception at 100 Mbps
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Chapter 5: Using the Client-side GMII Data Path
SFD
10 clock periods
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
Figure 5-12. At 1 Gbps speed,
5.
FCS
Figure 5-13. It
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UG155 March 24, 2008
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