Sgmii Standard Without The Optional Auto-Negotiation - Xilinx LogiCORE 1000BASE-X User Manual

Management Registers

SGMII Standard without the Optional Auto-Negotiation

The Registers provided for SGMII operation in this core are adaptations of those defined in
IEEE 802.3 clauses 37 and 22. In an SGMII implementation, two different types of links
exist. They are the SGMII link between the MAC and PHY (SGMII link) and the link across
the Ethernet Medium itself (Medium). See
SGMII link is available in registers that follow.
The state of the link across the Ethernet Medium itself is not directly available when SGMII
Auto-Negotiation is not present. For this reason, the status of the link and the results of the
PHYs Auto-Negotiation (for example, Speed and Duplex mode) must be obtained directly
from the management interface of connected PHY module. Registers at undefined
addresses are read-only and return 0s.
Table 9-29: MDIO Registers for 1000BASE-X with Auto-Negotiation
Register 0: SGMII Control
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Register Address
0
1
2,3
4
15
15 14 13 12 11 10
Reg 0
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Figure 10-2. Information about the state of the
Register Name
SGMII Control Register
SGMII Status Register
PHY Identifier
SGMII Auto-Negotiation Advertisement Register
SGMII Extended Status Register
MDIO Register 0: SGMII Control
9
8 7 6 5 4 0
R
145