Chapter 9: Configuration And Status; Mdio Management Interface; Mdio Bus System - Xilinx LogiCORE 1000BASE-X User Manual

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Configuration and Status
This chapter provides general guidelines for configuring and monitoring the Ethernet
1000BASE-X PCS/PMA or SGMII core, including a detailed description of the core
management registers. It also describes Configuration Vector and status signals, an
alternative to using the optional MDIO Management Interface.

MDIO Management Interface

When the optional MDIO Management Interface is selected, configuration and status of
the core is achieved by the Management Registers accessed through the serial
Management Data Input/Output Interface (MDIO). See
Chapter 3

MDIO Bus System

The MDIO interface for 1 Gbps operation (and slower speeds) is defined in IEEE 802.3,
clause 22. This two-wire interface consists of a clock (MDC) and a shared serial data line
(MDIO). The maximum permitted frequency of MDC is set at 2.5 MHz.
Figure 9-1
An Ethernet MAC is shown as the MDIO bus master (the Station Management (STA)
entity).
Two PHY devices are shown connected to the same bus, both of which are MDIO slaves
(MDIO Managed Device (MMD) entities).
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
for more information.
illustrates an example MDIO bus system.
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Chapter 9
"MDIO Management Interface" in
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