Figure 8-9: Clock Management With Multiple Core Instances With Virtex-5 Gtp - Xilinx LogiCORE 1000BASE-X User Manual

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Chapter 8: SGMII / Dynamic Standards Switching with RocketIO Transceivers
component_name_block
(Block Level)
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
component_name_block
(Block Level)
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2
Ethernet 1000BASE-X
PCS/PMA or
SGMII core
userclk
userclk2

Figure 8-9: Clock Management with Multiple Core Instances with Virtex-5 GTP

RocketIO Transceivers for SGMII
www.xilinx.com
BUFG
rocketio_wrapper_gtp_tile
REFCLKOUT
userclk2
(125 MHz)
FPGA
fabric
Rx
Elastic
Buffer
BUFR
FPGA
fabric
Rx
Elastic
Buffer
BUFR
rocketio_wrapper_gtp_tile
NC REFCLKOUT
userclk2
(125 MHz)
FPGA
fabric
Rx
Elastic
Buffer
BUFR
FPGA
fabric
Rx
Elastic
Buffer
BUFR
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
IBUFGDS
brefclkp
IPAD
IPAD
clkin
brefclkn
(125MHz)
rocketio_wrapper_gtp
Virtex-5
GTP
RocketIO
(0)
TXUSRCLK0
TXUSRCLK20
RXUSRCLK0
RXUSRCLK20
RXRECCLK0
CLKIN
Virtex-5
GTP
RocketIO
(1)
TXUSRCLK1
TXUSRCLK21
RXUSRCLK1
RXUSRCLK21
RXRECCLK1
rocketio_wrapper_gtp
Virtex-5
GTP
RocketIO
(0)
TXUSRCLK0
TXUSRCLK20
RXUSRCLK0
RXUSRCLK20
RXRECCLK0
CLKIN
Virtex-5
GTP
RocketIO
(1)
TXUSRCLK1
TXUSRCLK21
RXUSRCLK1
RXUSRCLK21
RXRECCLK1
UG155 March 24, 2008