Watchdog Timer - Analog Devices MicroConverter ADuC812 User Manual

ADuC812

WATCHDOG TIMER

The purpose of the watchdog timer is to generate a device reset
within a reasonable amount of time if the ADuC812 enters
an erroneous state, possibly due to a programming error.
The Watchdog function can be disabled by clearing the WDE
(Watchdog Enable) bit in the Watchdog Control (WDCON)
SFR. When enabled, the watchdog circuit will generate a system
reset if the user program fails to set the watchdog timer refresh
bits (WDR1, WDR2) within a predetermined amount of time
(see PRE2–0 bits in WDCON).
P R E 2 P R E 1
Bit Name
7 PRE2
6 PRE1
5 PRE0
4 —
3 WDR1
2 WDR2
1 WDS
1 WDE
Example
To set up the watchdog timer for a timeout period
of 2048 ms the following code would be used.
MOV WDCON,#0E0h ;2.048 second
;timeout period
SETB WDE ;enable watchdog timer
In order to prevent the watchdog timer timing out the timer
refresh bits need to be set before 2.048 seconds has elapsed.
SETB WDR1 ;refresh watchdog timer..
SETB WDR2 ; ..bits must be set in this
;order
P R E 0 —
Table IX. WDCON SFR Bit Designations
Description
Watchdog Timer Prescale Bits.
PRE2 PRE1 PRE0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Not Used.
Watchdog timer refresh bits, set sequentially to refresh the watchdog.
Watchdog Status Bit.
Set by the Watchdog Controller to indicate that a watchdog timeout has occurred.
Cleared by writing a "0" or by an external hardware reset. It is not cleared by a watchdog reset.
Watchdog Enable Bit.
Set by user to enable the watchdog and clear its counters.
The watchdog timer itself is a 16-bit counter. The watchdog
timeout interval can be adjusted via the PRE2–0 bits in
WDCON. Full Control and Status of the watchdog timer
function can be controlled via the watchdog timer control
SFR (WDCON).
WDCON
SFR Address
Power-On Default Value
Bit Addressable
W D R 1 W D R 2
Timeout Period (ms)
16
32
64
128
256
512
1024
2048
Watchdog Timer Control Register
C0H
00H
Yes
W D S W D E