Adccon2 - (Adc Control Sfr #2); Adccon3 - (Adc Control Sfr #3) - Analog Devices MicroConverter ADuC812 User Manual

ADuC812
ADCCON2 – (ADC Control SFR #2)
The ADCCON2 register controls ADC channel selection and conversion modes as detailed below.
SFR Address:
SFR Power On Default Value:
A D C I D M A
ocation Name
L
ADCCON2.7 ADCI
ADCCON2.6 DMA
ADCCON2.5 CCONV
ADCCON2.4 SCONV
ADCCON2.3 CS3
ADCCON2.2 CS2
ADCCON2.1 CS1
ADCCON2.0 CS0
ADCCON3 – (ADC Control SFR #3)
The ADCCON3 register gives user software an indication of ADC busy status.
SFR Address:
SFR Power On Default Value:
B U S Y R S V D
Bit Bit
Location Status
ADCCON3.7 BUSY
ADCCON3.6 RSVD
ADCCON3.5 RSVD
ADCCON3.4 RSVD
ADCCON3.3 RSVD
ADCCON3.2 RSVD
ADCCON3.1 RSVD
ADCCON3.0 RSVD
D8H
00H
C C O N V S C O
Table IV. ADCCON2 SFR Bit Designations
Description
The ADC interrupt bit (ADCI) is set by hardware at the end of a single ADC conversion cycle or at the
end of a DMA block conversion. ADCI is cleared by hardware when the PC vectors to the ADC Interrupt
Service Routine.
The DMA mode enable bit (DMA) is set by the user to enable a preconfigured ADC DMA mode opera-
tion. A more detailed description of this mode is given in the ADC DMA Mode section.
The continuous conversion bit (CCONV) is set by the user to initiate the ADC into a continuous mode of
conversion.
In this mode the ADC starts converting based on the timing and channel configuration already set up in
the ADCCON SFRs, the ADC automatically starts another conversion once a previous conversion
has completed.
The single conversion bit (SCONV) is set to initiate a single conversion cycle. The SCONV bit is
automatically reset to "0" on completion of the single conversion cycle.
The channel selection bits (CS3-0) allow the user to program the ADC channel selection under
software control. When a conversion is initiated the channel converted will be that pointed to by
these channel selection bits. In DMA mode the channel selection is derived from the channel ID
written to the external memory.
CS3 CS2 CS1 CS0 CH#
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 Temp Sensor
1 1 1 1 DMA STOP
All other combinations reserved
F5H
00H
R S V D R S V
Table V. ADCCON3 SFR Bit Designations
Description
The ADC busy status bit (BUSY) is a read-only status bit that is set during a valid ADC conversion or
calibration cycle. Busy is automatically cleared by the core at the end of conversion or calibration.
ADCCON3.0–3.6 are reserved (RSVD) for internal use. These bits will read as zero and should only
be written as zero by user software.
N V C S 3
D R S V D
C S 2 C S 1
R S V D R S V D
C S 0
R S V D