Analog Devices MicroConverter ADuC812 User Manual page 48

ADuC812
Parameter
EXTERNAL DATA MEMORY READ CYCLE
RD Pulsewidth
t
RLRH
t Address Valid after ALE Low
AVLL
t Address Hold after ALE Low
LLAX
RD Low to Valid Data In
t
RLDV
Data and Address Hold after RD
t
RHDX
Data Float after RD
t
RHDZ
t ALE Low to Valid Data In
LLDV
t Address to Valid Data In
AVDV
ALE Low to RD or WR Low
t
LLWL
Address Valid to RD or WR Low
t
AVWL
RD Low to Address Float
t
RLAZ
RD or WR High to ALE High
t
WHLH
ALE (O)
PSEN (O)
PORT 0 (I/O)
PORT 2 (O)
MCLK
t
LLWL
RD (O)
t
AVWL
t
LLAX
t
AVLL
A0–A7 (OUT)
t
AVDV
A16–A23
12 MHz Variable Clock
Min Max Min
400 6t
43 t
CK
48 t
CK
252
0 0
97
517
585
200 300 3t
203 4t
0
43 123 t
CK
t
LLDV
t
RLRH
t
RLDV
t
RHDX
t
RLAZ
DATA (IN)
A8–A15
Max Unit
– 100 ns
CK
– 40 ns
– 35 ns
5t – 165 ns
CK
ns
2t –70 ns
CK
8t – 150 ns
CK
9t – 165 ns
CK
– 50 3t + 50 ns
CK CK
– 130 ns
CK
0 ns
– 40 6t – 100 ns
CK
t
WHLH
t
RHDZ
Figure
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