ADuC812
Parameter
UART TIMING (Shift Register Mode)
t
Serial Port Clock Cycle Time
XLXL
t
Output Data Setup to Clock
QVXH
t
Input Data Setup to Clock
DVXH
t
Input Data Hold after Clock
XHDX
t
Output Data Hold after Clock
XHQX
ALE (O)
(OUTPUT CLOCK)
(OUTPUT DATA)
(INPUT DATA)
Min
700
300
0
50
TxD
0
t
QVXH
RxD
MSB
BIT6
t
DVXH
RxD
MSB
12 MHz
Typ
Max
Min
1.0
10t
CK
2t
CK
0
2t
CK
6
1
t
XHQX
BIT1
t
XHDX
BIT6
Variable Clock
Typ
Max
12t
CK
– 133
+ 133
– 117
t
XLXL
7
SET RI
OR
SET TI
LSB
BIT1
LSB
Unit
Figure
µs
55
ns
55
ns
55
ns
55
ns
55
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