Using The D/A Converter - Analog Devices MicroConverter ADuC812 User Manual

ADuC812

Using the D/A Converter

The on-chip D/A converter architecture consists of a resistor
string DAC followed by an output buffer amplifier, the func-
tional equivalent of which is illustrated in Figure 18. Details of
the actual DAC architecture can be found in U.S. Patent Num-
ber 5969657 (www.uspto.gov). Features of this architecture
include inherent guaranteed monotonicity and excellent differ-
ential linearity.
AV
DD
R
V
REF
R
R
R
R
As illustrated in Figure 18, the reference source for each DAC is
user selectable in software. It can be either AV
0-to-AV mode, the DAC output transfer function spans from
DD
0 V to the voltage at the AV
DAC output transfer function spans from 0 V to the internal
V or if an external reference is applied the voltage at the V
REF
pin. The DAC output buffer amplifier features a true rail-to-rail
output stage implementation. This means that, unloaded, each
output is capable of swinging to within less than 100 mV of both
AV and ground. Moreover, the DAC's linearity specification
DD
(when driving a 10 kΩ resistive load to ground) is guaranteed
through the full transfer function except codes 0 to 48, and, in
0-to-AV mode only, codes 3995 to 4095. Linearity degrada-
DD
tion near ground and V is caused by saturation of the output
DD
amplifier, and a general representation of its effects (neglecting
offset and gain error) is illustrated in Figure 19. The dotted line
in Figure 19 indicates the ideal transfer function, and the solid
line represents what the transfer function might look like with
endpoint nonlinearities due to saturation of the output amplifier.
Note that Figure 19 represents a transfer function in 0-to-V
mode only. In 0-to-V mode (with V
REF
nonlinearity would be similar, but the upper portion of the
transfer function would follow the "ideal" line right to the end
(V in this case, not V ), showing no signs of endpoint lin-
REF DD
earity errors.
ADuC812
OUTPUT
BUFFER
8
HIGH-Z
DISABLE
(FROM MCU)
or V
DD REF.
pin. In 0-to-V mode, the
DD REF
< V ) the lower
REF DD
V
DD
V – 50mV
DD
V – 100mV
DD
100mV
50mV
0mV
000 HEX
The endpoint nonlinearities conceptually illustrated in Figure 19
get worse as a function of output loading. Most of the ADuC812's
data sheet specifications assume a 10 kΩ resistive load to ground
at the DAC output. As the output is forced to source or sink
more current, the nonlinear regions at the top or bottom
(respectively) of Figure 19 become larger. With larger current
demands, this can significantly limit output voltage swing.
Figure 20 and Figure 21 illustrate this behavior. It should be noted
In
that the upper trace in each of these figures is only valid for an
output range selection of 0-to-AV
loading will not cause high-side voltage drops as long as the
reference voltage remains below the upper trace in the correspond-
REF
ing figure. For example, if AV
high-side voltage will not be affected by loads less than 5 mA.
But somewhere around 7 mA the upper curve in Figure 21 drops
below 2.5 V (V
REF
output will not be capable of reaching V
5
DAC LOADED WITH 0FFF HEX
4
3
DD
2
1
DAC LOADED WITH 0000 HEX
0
0
. In 0-to-V
DD
= 3 V and V
DD
) indicating that at these higher currents the
.
REF
5 10
SOURCE/SINK CURRENT – mA
FFF HEX
mode, DAC
REF
= 2.5 V, the
REF
15