Data General Corporation (DGC) has prepared this manual for use by DGC personnel and customers as a guide to the proper installation, operation, and
maintenance of DGC equipment and software. The drawings and specifications contained herein are the property of DGC and shall neither be reproduced in whole or
in part without DGC's prior written approval nor be implied to grant any license to make, use, or sell equipment manufactured in accordance herewith.
INTERCONNECTION WITH SYSTEM
The memory communicates with the rest of the system
via its A and B connectors to the backpanel. Tables 12.1
through
12.6
list
each
signal
either
generated
or
received
by
a
memory
board
together
with
the
backpanel location of the signal.
Signal
Back- | Source | Destination | Description
BMEMCLK
A43
CPU
Memory, FPU
10 MHZ square
wave MEMIN
B1OCLK
A35
Power
CPU, Memory, | 10 MHZ square
Supply
FPU
wave
B20CLK
A39
Power
CPU, Memory | 20 MHZ square
Supply
wave
* See Appendix D for a timing diagram of the system
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