Data General NOVA 4/S Manual page 117

Data General Corporation (DGC) has prepared this manual for use by DGC personnel and customers as a guide to the proper installation, operation, and
maintenance of DGC equipment and software. The drawings and specifications contained herein are the property of DGC and shall neither be reproduced in whole or
in part without DGC's prior written approval nor be implied to grant any license to make, use, or sell equipment manufactured in accordance herewith.
TIME IN 0 100 200 300 400 500 600 700 800 900 1000
NANOSECONDS | | | |
memstarT J, LJ, 1
MEMIN —LADDRESST ADATA [ADDRESS]
BOARDSELECT _J =U CULt:~<"<—t~'"'
MODARDY————@L _S
MODASELO SL
RAORENBMODA —___
CADRENBMODA A ROW _ACOL
ADR <0-6>A — L_ADDR | ADDR J
Di<0-18> [VALID DATA-IN TIME]
MODBRDY mi J
MODBSELO SL
RADRENBMODB _|
CADRENBMODB 3 ROW La
ADR <0-6>B [ ADDR J ADDR _ ]
MODBRASO J L
MODBCAS f at
MEMOUT {DATA OUT
DG-05950
Write To Module A - Read From Module B
Figure 12.2. TIMING DIAGRAM
ARCHITECTURE
The block diagram, Figure 12.3, shows the principal
components plus the control and data paths of the RAM
memory boards. In addition to the RAM array, the
memory boards contain:
© Two parallel data buses (memory in and memory
e An interface timing generator
e An input buffer
105
Board, module, and bank select logic
Refresh logic
Module A, B, C, and D timing logic
Row and column address latches for each module
A four-to-one output multiplexer
Four output registers
A memory out bus driver