Data General NOVA 4/S Manual page 112

Data General Corporation (DGC) has prepared this manual for use by DGC personnel and customers as a guide to the proper installation, operation, and
maintenance of DGC equipment and software. The dra wings and specifications contained herein are the property of DGC and shall neither be reproduced in whole or
in part without DGC's prior written approva) nor be implied to grant any license to make, use, or sell equipment manufactured in accordance herewith.
Table 11.4
MEMORY READ DATA
Signal Back- | Source | Destination | Description
Pin
MEMOUTO A7 Memory CPU, FPU High-order data
FPU CPU bit
MEMOUT1 AQ Memory CPU, FPU Data bit
FPU CPU
MEMOUT2 A13 Memory CPU, FPU Data bit
FPU CPU
MEMOUT3 Alt Memory CPU, FPU Data bit
FPU CPU
MEMOUT4 A15 Memory CPU, FPU Data bit
FPU CPU
MEMOUTS5 A117 Memory CPU, FPU Data bit
FPU CPU
MEMOUTE6 A21 Memory CPU, FPU Data bit
FPU CPU
MEMOUT7 A19 Memory {|CPU, FPU Data bit
FPU CPU
MEMOUT8 A26 Memory ;CPU, FPU Data bit
MEMOUTS A22 Memory CPU, FPU Data bit
FPU CPU
MEMOUT 10 Ai2 Memory | CPU, FPU Data bit
FPU CPU
MEMOUT 11 Ai8 Memory {CPU, FPU Data bit
MEMOUT 12 A28 Memory CPU, FPU Data bit
MEMOUT13 A24 Memory CPU, FPU Data bit
FPU CPU
MEMOUT 14 A16 Memory CPU, FPU Data bit
FPU CPU
MEMOUT 15 A20 Memory CPU, FPU Low-order data
FPU CPU bit
MEMOUT 16 A31 Memory - Reserved for
MEMOUT17 A30 Memory =~ Reserved for
MEMOUT 18 A29 Memory - Reserved for
future use
MEMOUT19 A23 Memory _ Reserved for
MEMOUT20 A27 Memory _ Reserved for
Table 11.5
DATA CHANNEL AND INTERRUPT SIGNALS*
Signal Back- | Source | Destination | Description
DCHA A60 CPU 1/0 Data channel
acknowledge
DCHi B37 CPU /O Data channel
DCHO B33 cpu /O Data channel
output
DCHMO B17 1/0 CPU Data channel
mode select
DCHR B35 VO CPU Data channel
FASTDCH A95 CPU /0 High speed
INTA A40 CPU 1/0, FPU Interrupt
acknowledge
INTR B29 0, FPU {CPU Interrupt
MSKO A38 CPU 1/0, FPU Mask out
ROQENB B41 CPU 1/0, FPU Request
synchronizing
SELB A82 1/0 CPU Selected device
SELD A80 1/0, FPU | CPU Selected I/O
overfiow,
underflow, or
divide by zero
* See Interface Designer's Reference (DGC No. 015-000031), for more
information on how the I/O signals function.
Signal Back- | Source |Destination | Description
Pin
DSO A72 CPU 1/0, FPU Device select bit O
DS1 A68 CPU 1/0, FPU Device select bit 1
DS2 A66 CPU 1/O, FPU Device select bit 2
DS3 A46 CPU 1/0, FPU Device select bit 3
DSs4 A62 CPU 1/0, FPU Device select bit 4
DS5 A64 CPU 1/0, FPU Device select bit 5
* See Interface Designer's Reference (DGC No. 015-000031), for more
information on how the I/O signals function.
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