Data General NOVA 4/S Manual page 119

~ OPERATIONS
When the CPU asserts the MEMSTART signal, all the
memory boards in the system examine the address
appearing on the memory address/data bus MEMIN
different size memory boards as shown below.
256K Byte Board
MSsB LSB
190123456789 10 11 12 13 14 15
1 Ce JS. _ A
BANK SELECT
128K Byte Board
MSB LSB
190123456789 10 11 12 13 14 15
—; J ~, I~
ROW ADDRESS = COLUMNADDRESS MODULE
BOARD SELECT
MSB LSB
' {
19012345 67 89 10 11 12 13 14 15
BOARD | ROWADDRESS COLUMNADDRESS MODULE
0123456789 10 11 12 13 14 15
BOARD ROW ADDRESS COLUMNADDRESS MODULE
Since the 256K byte board is normally the only board in
the system when present, it does not use the board select
lines shown above for the remaining boards. The select
logic for the remaining boards examines the board select
lines to determine if the address is within the range
assigned to the board by the on-board jumper
configuration. If it is, the select logic then examines the
module and bank select lines. Note that there are no bank
select lines on the 128K byte and 32K byte boards since
they contain only bank 0. The interface timing generator
controls the select logic timing.
107
transferred to the selected module's row address latch to
determine the RAM array row address. The information
on the column address lines is transferred to the selected
module's column address latch to determine the RAM
array column address. These addresses are both
transferred to the selected module and bank on the
CADRENBMOD <A,B,C,D> transfer the row address
transferred to the data latch. The MEMWRITE signal
generates the MOD <A,B,C,D> WE signal via the
selected column latch. This signal enables the output of the
data latch, DI <0-15>, to be written into the addressed
RAM location.
In a memory read operation, the data contained in the
selected RAM location appears on the DO <A,B,C,D>
four-to-one output multiplexer selects this data from the
appropriate module and transfers it via the ADO <0-15>
lines to one of four output registers. The output register
transfers the data to the bus driver via the IDO <0-15>
lines. The data is then driven onto the memory out bus
The output registers called W, X, Y, and Z, are selected
consecutively. For example, if register Y was used for a
memory operation, register Z will be used for the next, and
then register W and so on. This is done independently of
the module and bank selection.
When all four modules are idle (i.e., ready to accept a read
or write command), the refresh logic is enabled. Memory
refreshing occurs approximately every 25ysec on the 32K
byte and 64K byte boards and approximately every 13sec
on the 128K byte and 256K byte boards. The refresh logic
generates refresh control signals which force the module
control logic to enable the row address inputs of the RAM
array. The refresh logic then generates its own address
which are transferred to the RAM array.
If the system has the battery back-up option, a power fail
causes the low state of the PWROK signal to enable the
refresh logic. Refreshing is the only operation performed
by the memories when the system is being powered by the
battery back-up option. If the system does not have the
battery back-up option, then a power fail causes the
contents of memory to be lost.
If the CPU selects a memory board while it is performing a
read, write or refresh operation, the memory board sends