Data General NOVA 4/S Manual page 111

lll either
generated or received by the CPU board together with
Signal Back- | Source | Destination | Description
Pin
(AC line
margining logic.
* See Appendix D for a timing diagram of the system clock signals.
Table 11.2
Signal Back- | Source {Destination | Description
Pin
BMEMCLK* A43 CPU Memory, FPU | 10 MHZ Square
wave MEMIN
bus clock
INHSEL B83 CPU Memory Prevents
memory from
during a
CPU-FPU data
transfer.
MEMOK A96 Power CPU +12 MEM
MEMSTART A55 CPU Memory Memory
MEMWAIT A32 - CPU Reserved for
operation
starting
* See Appendix D for a timing diagram.
Signal Back- |Source | Destination | Description
Pin
high-order data
MEMIN3 B18 CPU Memory, FPU Physical
MEMIN4 B26 CPU Memory, FPU Physical
FPU Memory address bit or
data bit
MEMINS B24 CPU Memory, FPU Physical
FPU Memory address bit or
data bit
MEMING B22 CPU Memory, FPU Physical
FPU Memory address bit or
data bit
FPU Memory address bit or
data bit
MEMIN8 B28 CPU Memory, FPU | Physical
data bit
MEMINQ B30 CPU Memory, FPU | Physical
data bit
MEMIN10 B32 CPU Memory, FPU | Physical
data bit
MEMIN 11 B42 CPU Memory, FPU Physical
FPU Memory address bit or
data bit
MEMIN12 B47 CPU Memory, FPU Physical
FPU Memory address bit or
data bit
MEMIN13 B45 CPU Memory, FPU | Physical
data bit
MEMIN 14 B44 CPU Memory, FPU Physical
FPU Memory address bit or
data bit
MEMIN15 B43 CPU Memory, FPU Low-order
address bit or
low-order data
bit
MEMIN16 B10 CPU Memory Reserved for
MEMIN17 B9 CPU Memory Reserved for
MEMIN18 BS CPU Memory Reserved for
MEMIN19 B7 CPU Memory High-order
physical
address bit