Data General NOVA 4/S Manual page 103

Data General Corporation (DGC) has prepared this manual for use by DGC personnel and customers as a guide to the proper installation, operation, and
maintenance of DGC equipment and software. The drawings and specifications contained herein are the property of DGC and shall neither be reproduced in whole or
in part without DGC's prior written approval nor be implied to grant any license to make, use, or sell equipment manufactured in accordance herewith.
The 16-bit wide, unidirectional ALUIN bus. carries
information to the data manipulation unit from all major
units of the CPU board.
The 16-bit wide, unidirectional ALUOQUT bus carries
information from the data manipulation unit to all major
units of the CPU board.
The 16-bit wide, unidirectional PFP bus carries
information to the CPU from the prefetch processor.
System Buses
The 17-bit wide MEMIN bus is a unidirectional path
which carries both 17-bit memory addresses and 16-bit
data words from the CPU to memory. When a floating
point unit (FPU) is present, this bus also carries data words
from the CPU to the FPU. Associated with the MEMIN
bus are the following memory control lines: MEMSTART
'(start memory), MEMSORRY (memory busy), MEMWRITE
(memory write operation), INHSEL (inhibit memory start),
BMEMCLK (memory bus clock), and MEMWAIT (delay
memory access).
The 16-bit wide MEMOUT bus is a undirectional path
which carries 16-bit data words from the memory to the
CPU. When an FPU is present, this bus also carries data
words from the FPU to the CPU and from memory to the
The 48-line I/O bus carries information between the CPU
and the system I/O controllers. This bus includes the
16-bit wide, bidirectional data bus (DATA<0-15> ) which
transfers all data. The remaining 32 lines carry
programmed I/O, program interrupt, data channel, and
system control signals.
Control Processor
The control processor executes the CPU instruction set
by interpreting each assembly language instruction as a
macroinstruction. It decodes the macroinstruction and
then executes the appropriate sequence of
microinstructions stored in the control store ROMs to
perform the specified function. When executed, the
microinstructions control the data paths and _ the
operation of the data manipulation unit as well as the
PFP, the memory, input/output, and the optional FPU.
Besides the PFP and the MMPU (NOVA 4/X only), the
control processor consists of the following major units:
e System timing logic
e Instruction register
e Instruction decode logic
e Starting address generator
e Control store
® Test multiplexors
® Microcode decode logic
e Memory control logic
e FPU control logic
11.2.
interconnection of these units is shown in Figure