Data General NOVA 4/S Manual page 106

Data General Corporation (DGC) has prepared this manual for use by DGC personnel and customers as a guide to the proper installation, operation, and
maintenance of DGC equipment and software. The drawings and specifications contained herein are the property of DGC and shall neither be reproduced in whole or
in part without DGC's prior written approval nor be implied to grant any license to make, use, or sell equipment manufactured in accordance herewith.
Memory Control Logic
This control section initiates all memory read and write
operations specified by the information appearing on
the uIR bus. In a system with an FPU, memory read and
write operations are also used to transfer data between the
FPU and memory and between the CPU and the FPU (see
Chapter 13).
As shown in Figure 11.2, the CPU is connected to the
MEMIN bus via the PFP memory address register and
data address/write data register. The CPU is connected to
the MEMOUT bus via the PFP instruction store and the
The CPU allows 500 ns for a read operation and 200 ns for
a write operation. Both operations proceed in two phases:
an address transfer and a data transfer.
During the address phase of either a read or write
operation, the memory control logic drives a 17-bit address
onto the MEMIN bus and drives the MEMSTART signal to
the low state. If the PFP is fetching an instruction, the
address is supplied by the PFP memory address register;
otherwise, the address is supplied by the address/write
data register. If the memory is busy, it drives MEMSORRY
to the low state to freeze the BMEMCLK until the memory
is ready to start another read or write operation.
During the data transfer phase of a read operation, the
CPU loads the 16-bit word appearing on the MEMOUT bus
into the PFP's instruction store if the PFP requested the
memory operation; otherwise, it loads the word into the
central processing element of the data manipulation unit.
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During the data transfer phase of a write operation, the
CPU drives the data onto the MEMIN bus from the data
address/write data register.
FPU Control Logic
In a system with an FPU, the FPU control logic initiates
the operation of the FPU under the direction of
information appearing on the uIR bus and _ status
information from the FPU. It informs the FPU when the
control processor decodes a floating point instruction and
when the memory control logic initiates a memory
operation to transfer data between the FPU and the CPU
or memory (see Chapter 13).
1/O Logic
The I/O logic governs the operation of the I/O bus
drivers and receivers which connect the CPU to the
system I/O bus. It performs the following functions:
® Generates the I/O synchronizing signal, RQENB
e Receives both I/O interrupt requests and data
channel requests
e Supports programmed I/O and data channel
transactions
The NOVA 4's I/O bus adheres to the standard NOVA
I/O bus conventions. For more information, see the
Interface Designer's Reference (DGC No. 015-000031).