Revision History - Alpha Data ADM-PCIE-8K5 User Manual

ADM-PCIE-8K5 User Manual

Revision History

Date
25 Feb 2016
29 Mar 2016
4 May 2016
6 Jun 2016
6 Jan 2017
7 Feb 2017
7 Mar 2017
1 May 2017
21 Jun 2017
28 Jun 2017
18 Sep 2017
20 Dec 2018
Revision Table
ad-ug-1319_v1_12.pdf
Revision Changed By
0.1 K. Roth
1.0 K. Roth
1.1 K. Roth
1.2 K. Roth
1.3 K. Roth
1.4 K. Roth
1.5 K. Roth
1.6 K. Roth
1.7 K. Roth
1.8 D. Flint
1.9 K. Roth
1.10 K. Roth
Nature of Change
Initial Draft
Initial Release, updated
photos, updated SDK reference.
Updated DDR4 SDRAM
speed while include DBI feature as required and added IP
core setup list, updated Configuration From Flash Memory
by adding Vivado hardware manager setup list, corrected
LED Details.
Added Building and Programming Configuration
Removed section: Configuration From Flash Memory,
Updated LED figure in LEDs
Added available power by rail table to
Added section: Custom Flash Write
Firefly part numbers in FireFly, Added note about PCIe RX
equalization options.
Removed references to automatic temperature monitoring
and protection.
Corrected firefly clock speed in
scaling factor note regarding current measurement results in
System Monitor.
VCC_BRAM removed from 1.8V row of table in
Requirements, Scaled thermal performance graph to match
innacuracies of current measurement circuit
Performance, corrected SFP0 and SFP1 location shown in
section SFP+, added MIG IP setup requirements rev2 +
newer PCBs, updated USB Front Panel Interface
avr2util instructions.
Updated all reference to DDR4 speeds at 8G to be 2400MT/
s and 16g to be 1866MT/s.
Updated Thermal Performance
accurate thermal tests.
Updated Switches for PCIe I2C isolation function added at
rev4 PCB, Clocking updated with maximum programable
frequency of 312.5MHz, Updated
number summary for the custom csv files, updated
state that the Si5328 is not fitted only on rev3 and earlier.
Updated SFP+ details on Si5328, updated
that the direct connect signals may always be used.
Fabric Clock to CMOS, updated
to specify DDR4-2133 as maximum
Power Requirements,
Interface, Updated
Clock Topology, Added
Power
Thermal
with results from more
DDR4 SDRAM
GPIO
Images,
to include
timing
SFP+ to
to clarify
Page 37