ADM-PCIE-9V8 User Manual 1 Introduction The ADM-PCIE-9V8 is an ultra-low latency high-performance reconfigurable computing card intended for low latency trading applications, featuring a screened AMD Virtex UltraScale+ Plus FPGA with low latency transceivers and four QSFP-DD cages. Figure 1 : ADM-PCIE-9V8 Product Photo 1.1 Key Features...
ADM-PCIE-9V8 User Manual 2 Board Information 2.1 Physical Specifications The ADM-PCIE-9V8 complies with PCI Express CEM revision 3.0. Description Measure PCB Dy 100.15 mm Total Dx 239.0 mm PCB Dz 1.6 mm Table 1 : Mechanical Dimensions (PCB only) Description...
2.2 Chassis Requirements 2.2.1 PCI Express The ADM-PCIE-9V8 is capable of PCIe Gen 3 with 8 lanes, using the AMD Integrated Block for PCI Express. 2.2.2 Mechanical Requirements An 8 or 16 lane physical PCIe slot is required for mechanical compatibility.
If the FPGA core temperature exceeds 105 degrees Celsius, the FPGA design will be cleared to prevent the card from over-heating. The ADM-PCIE-9V8 comes with a heat sink to help avoid thermal overstress of FPGA, since it is typically the hottest point on the card. The FPGA die temperature must remain under 100 degrees Celsius. To calculate the FPGA die temperature, take your application power, multiply by Theta JA from the table below, and add to your system internal ambient temperature.
3 Functional Description 3.1 Overview The ADM-PCIE-9V8 is a versatile reconfigurable computing platform with an Ultra Low Latency Virtex UltraScale+ VU2P FPGA, a Gen3x8 PCIe interface, four QSFP-DD cages, four Samtec FireFly connectors, an isolated input for a timing synchronization pulse, a 12 pin header for general purpose use (clocking, control pins, debug, etc.), front panel LEDs, and a robust system monitor.
ADM-PCIE-9V8 User Manual 3.1.1 Switches The ADM-PCIE-9V8 has an octal DIP switch SW1, located on the rear side of the board. The function of each switch in SW1 is detailed below: Figure 5 : Switches Factory Switch Function OFF State...
ADM-PCIE-9V8 User Manual 3.1.2 LEDs There are 9 LEDs on the ADM-PCIE-9V8, 6 of which are general purpose and whose meaning can be defined by the user. The other 3 have fixed functions described below: User LEDs Status LEDs LED_G2...
FPGA fabric. The reprogrammable clocks from the LMK61E2 are reconfigurable from the front panel Interface by using Alpha Data’s avr2util utility. This allows the user to configure almost any arbitrary clock frequency during application run time. The maximum clock frequency for the LMK61e2 is 900MHz. There is also an of embedding IP into the FPGA design that permits programmable clock re-configuration via PCIe or from within the FPGA.
ADM-PCIE-9V8 User Manual 3.2.1 LMK61E2 The ADM-PA120 uses the LMK61E2 for arbitrary clock frequency synthesis. For complete technical details, please reference the datasheet: https://www.ti.com/lit/ds/symlink/lmk61e2.pdf The ADM-PA120 uses two LMK61E2 devices in the clock architecture. These can be accessed through either the USB or PCIe link using the AVR2UTIL application.
ADM-PCIE-9V8 User Manual 3.2.2 Si5324 Please note that some net names in the design refer to the SI5324 as an SI5328. These devices are footprint and functionally compatible. The SI5324E-C-GM was chosen at the time of production due to availability concerns and is the part fitted on every board.
ADM-PCIE-9V8 User Manual 3.2.5 Programming Clock (EMCCLK) A 100MHz clock (net name EMCCLK_B) is fed into the EMCCLK pin to drive the SPI flash device during configuration of the FPGA. Note that this is not a global clock capable IO pin.
3.3 PCI Express The ADM-PCIE-9V8 is capable of PCIe Gen 3 with 8 lanes. The FPGA drives these lanes directly using the Integrated PCI Express block from AMD. Negotiation of PCIe link speed and number of lanes used is generally automatic and does not require user intervention.
ADM-PCIE-9V8 User Manual 3.4 QSFP-DD Trace lengths for the QSFP links and the associated estimated propagation delay for each lane is listed in appendix Propagation Delays. These delays were calculated using the estimated propagation delay of Megtron 6 PCB laminate, which is 5.85ps/mm.
ADM-PCIE-9V8 User Manual 3.5 FireFly Trace lengths for the FireFly links and the associated estimated propagation delay for each lane is listed in appendix Propagation Delays. These delays were calculated using the estimated propagation delay of Megtron 6 PCB laminate, which is 5.85ps/mm.
3.6 System Monitor The ADM-PCIE-9V8 has the ability to monitor its own temperature and the voltages and currents of certain power supply rails, in order to provide an indication of board health. The monitoring is implemented using an Atmel AVR microcontroller.
ADM-PCIE-9V8 User Manual 3.6.1 System Monitor Status LEDs LEDs D7 (Red) and D9 (Green) indicate the card health status. LEDs Status Green Running and no alarms Green + Red Standby (Powered off) Flashing Green + Flashing Red Attention - critical alarm active...
The ADM-PCIE-9V8 utilizes the Digilent USB-JTAG converter box which is supported by the AMD software tool suite. Simply connect a micro-USB AB type cable between the ADM-PCIE-9V8 USB port and a host computer with Vivado installed. Vivado Hardware Manager will automatically recognize the FPGA and allow you to configure the FPGA and the SPI configuration Flash memory.
Pins 1 and 2 of J1 can be used as an isolated timing input signal (up to 25MHz). Applications can either directly connect to the GPIO connector, or Alpha Data can provide a cabled solution with an SMA or similar connector on the front panel.
ADM-PCIE-9V8 User Manual For pin locations, see signal name ISO_CLK in Complete Pinout Table. The signal is isolated through a optical isolator part number TLP2367 with 220 ohm of series resistance. 3.10 User EEPROM A 2Kb I2C user EEPROM is provided for storing MAC addresses or other user information. The EEPROM is part number CAT34C02HU4IGT4A The address pins A2, A1, and A0 are all strapped to a logical '0'.
ADM-PCIE-9V8 User Manual Signal Name Pin Name Bank Voltage Number BE13 TMS_0 1.8 (LVCMOS18) AU25 USER_LED_G0_1V8 IO_L16P_T2U_N6_QBC_AD3P_66 1.8 (LVCMOS18) AU24 USER_LED_G1_1V8 IO_L16N_T2U_N7_QBC_AD3N_66 1.8 (LVCMOS18) AV23 USER_LED_G2_1V8 IO_L17P_T2U_N8_AD10P_66 1.8 (LVCMOS18) AV22 USER_LED_G3_1V8 IO_L17N_T2U_N9_AD10N_66 1.8 (LVCMOS18) AU21 USER_LED_G4_1V8 IO_L18P_T2U_N10_AD2P_66 1.8 (LVCMOS18) AV21...
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ADM-PCIE-9V8 User Manual Revision History Date Revision Changed By Nature of Change Initial Release 12-Oct-2023 K. Roth Address: Suite L4A, 160 Dundee Street, Address: 10822 West Toller Drive, Suite 250 Edinburgh, EH11 1DQ, UK Littleton, CO 80127 Telephone: +44 131 558 2600...
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