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Alpha Data ADM-PCIE-9V8 User Manual

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ADM-PCIE-9V8
User Manual
Document Revision: 1.0
October 12th 2023

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Summary of Contents for Alpha Data ADM-PCIE-9V8

  • Page 1 ADM-PCIE-9V8 User Manual Document Revision: 1.0 October 12th 2023...
  • Page 2 ADM-PCIE-9V8 User Manual © 2023 Copyright Alpha Data Parallel Systems Ltd. All rights reserved. This publication is protected by Copyright Law, with all rights reserved. No part of this publication may be reproduced, in any shape or form, without prior written consent from Alpha Data Parallel Systems Ltd.

  • Page 3: Table Of Contents

    ADM-PCIE-9V8 User Manual Table Of Contents Introduction ............................1 Key Features ..........................1 Order Code ............................ 1 Board Information ..........................2 Physical Specifications ........................2 Chassis Requirements ........................3 2.2.1 PCI Express ..........................3 2.2.2 Mechanical Requirements ......................3 2.2.3 Power Requirements .........................
  • Page 4 Table 9 Complete Pinout Table ........................21 Table 10 Complete Pinout Table ........................27 List of Figures Figure 1 ADM-PCIE-9V8 Product Photo ......................1 Figure 2 ADM-PCIE-9V8 Fully Assembled ....................... 2 Figure 3 Thermal Performance ........................4 Figure 4 ADM-PCIE-9V8 Block Diagram ......................5 Figure 5 Switches .............................

  • Page 5: Introduction

    ADM-PCIE-9V8 User Manual 1 Introduction The ADM-PCIE-9V8 is an ultra-low latency high-performance reconfigurable computing card intended for low latency trading applications, featuring a screened AMD Virtex UltraScale+ Plus FPGA with low latency transceivers and four QSFP-DD cages. Figure 1 : ADM-PCIE-9V8 Product Photo 1.1 Key Features...

  • Page 6: Board Information

    ADM-PCIE-9V8 User Manual 2 Board Information 2.1 Physical Specifications The ADM-PCIE-9V8 complies with PCI Express CEM revision 3.0. Description Measure PCB Dy 100.15 mm Total Dx 239.0 mm PCB Dz 1.6 mm Table 1 : Mechanical Dimensions (PCB only) Description...

  • Page 7: Chassis Requirements

    2.2 Chassis Requirements 2.2.1 PCI Express The ADM-PCIE-9V8 is capable of PCIe Gen 3 with 8 lanes, using the AMD Integrated Block for PCI Express. 2.2.2 Mechanical Requirements An 8 or 16 lane physical PCIe slot is required for mechanical compatibility.

  • Page 8: Thermal Performance

    If the FPGA core temperature exceeds 105 degrees Celsius, the FPGA design will be cleared to prevent the card from over-heating. The ADM-PCIE-9V8 comes with a heat sink to help avoid thermal overstress of FPGA, since it is typically the hottest point on the card. The FPGA die temperature must remain under 100 degrees Celsius. To calculate the FPGA die temperature, take your application power, multiply by Theta JA from the table below, and add to your system internal ambient temperature.

  • Page 9: Functional Description

    3 Functional Description 3.1 Overview The ADM-PCIE-9V8 is a versatile reconfigurable computing platform with an Ultra Low Latency Virtex UltraScale+ VU2P FPGA, a Gen3x8 PCIe interface, four QSFP-DD cages, four Samtec FireFly connectors, an isolated input for a timing synchronization pulse, a 12 pin header for general purpose use (clocking, control pins, debug, etc.), front panel LEDs, and a robust system monitor.

  • Page 10: Switches

    ADM-PCIE-9V8 User Manual 3.1.1 Switches The ADM-PCIE-9V8 has an octal DIP switch SW1, located on the rear side of the board. The function of each switch in SW1 is detailed below: Figure 5 : Switches Factory Switch Function OFF State...

  • Page 11: Leds

    ADM-PCIE-9V8 User Manual 3.1.2 LEDs There are 9 LEDs on the ADM-PCIE-9V8, 6 of which are general purpose and whose meaning can be defined by the user. The other 3 have fixed functions described below: User LEDs Status LEDs LED_G2...

  • Page 12: Clocking

    FPGA fabric. The reprogrammable clocks from the LMK61E2 are reconfigurable from the front panel Interface by using Alpha Data’s avr2util utility. This allows the user to configure almost any arbitrary clock frequency during application run time. The maximum clock frequency for the LMK61e2 is 900MHz. There is also an of embedding IP into the FPGA design that permits programmable clock re-configuration via PCIe or from within the FPGA.

  • Page 13: Lmk61E2

    ADM-PCIE-9V8 User Manual 3.2.1 LMK61E2 The ADM-PA120 uses the LMK61E2 for arbitrary clock frequency synthesis. For complete technical details, please reference the datasheet: https://www.ti.com/lit/ds/symlink/lmk61e2.pdf  The ADM-PA120 uses two LMK61E2 devices in the clock architecture. These can be accessed through either the USB or PCIe link using the AVR2UTIL application.

  • Page 14: Si5324

    ADM-PCIE-9V8 User Manual 3.2.2 Si5324 Please note that some net names in the design refer to the SI5324 as an SI5328. These devices are footprint and functionally compatible. The SI5324E-C-GM was chosen at the time of production due to availability concerns and is the part fitted on every board.

  • Page 15: Programming Clock (Emcclk)

    ADM-PCIE-9V8 User Manual 3.2.5 Programming Clock (EMCCLK) A 100MHz clock (net name EMCCLK_B) is fed into the EMCCLK pin to drive the SPI flash device during configuration of the FPGA. Note that this is not a global clock capable IO pin.

  • Page 16: Pci Express

    3.3 PCI Express The ADM-PCIE-9V8 is capable of PCIe Gen 3 with 8 lanes. The FPGA drives these lanes directly using the Integrated PCI Express block from AMD. Negotiation of PCIe link speed and number of lanes used is generally automatic and does not require user intervention.

  • Page 17: Qsfp-Dd

    ADM-PCIE-9V8 User Manual 3.4 QSFP-DD Trace lengths for the QSFP links and the associated estimated propagation delay for each lane is listed in appendix Propagation Delays. These delays were calculated using the estimated propagation delay of Megtron 6 PCB laminate, which is 5.85ps/mm.

  • Page 18: Firefly

    ADM-PCIE-9V8 User Manual 3.5 FireFly Trace lengths for the FireFly links and the associated estimated propagation delay for each lane is listed in appendix Propagation Delays. These delays were calculated using the estimated propagation delay of Megtron 6 PCB laminate, which is 5.85ps/mm.

  • Page 19: System Monitor

    3.6 System Monitor The ADM-PCIE-9V8 has the ability to monitor its own temperature and the voltages and currents of certain power supply rails, in order to provide an indication of board health. The monitoring is implemented using an Atmel AVR microcontroller.

  • Page 20: System Monitor Status Leds

    ADM-PCIE-9V8 User Manual 3.6.1 System Monitor Status LEDs LEDs D7 (Red) and D9 (Green) indicate the card health status. LEDs Status Green Running and no alarms Green + Red Standby (Powered off) Flashing Green + Flashing Red Attention - critical alarm active...

  • Page 21: Usb Interface

    The ADM-PCIE-9V8 utilizes the Digilent USB-JTAG converter box which is supported by the AMD software tool suite. Simply connect a micro-USB AB type cable between the ADM-PCIE-9V8 USB port and a host computer with Vivado installed. Vivado Hardware Manager will automatically recognize the FPGA and allow you to configure the FPGA and the SPI configuration Flash memory.

  • Page 22: Building And Programming Configuration Images

    ADM-PCIE-9V8 User Manual 3.8.1.1 Building and Programming Configuration Images Generate a bitfile with these constraints (see xapp1233): • set_property BITSTREAM.GENERAL.COMPRESS TRUE [ current_design ] • set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design] • set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] • set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] •...

  • Page 23: Gpio Connector

    Pins 1 and 2 of J1 can be used as an isolated timing input signal (up to 25MHz). Applications can either directly connect to the GPIO connector, or Alpha Data can provide a cabled solution with an SMA or similar connector on the front panel.

  • Page 24: User Eeprom

    ADM-PCIE-9V8 User Manual For pin locations, see signal name ISO_CLK in Complete Pinout Table. The signal is isolated through a optical isolator part number TLP2367 with 220 ohm of series resistance. 3.10 User EEPROM A 2Kb I2C user EEPROM is provided for storing MAC addresses or other user information. The EEPROM is part number CAT34C02HU4IGT4A The address pins A2, A1, and A0 are all strapped to a logical '0'.

  • Page 25: Appendix A Propagation Delays

    ADM-PCIE-9V8 User Manual Appendix A: Propagation Delays Trace Delay Trace Length Signal Name Pin Name (ps) (mm) Number 52.9 QSFP_1_RX3_N MGTFRXN3_131 53.1 QSFP_1_RX3_P MGTFRXP3_131 55.6 AL45 QSFP_2_RX3_P MGTFRXP3_126 55.6 AL46 QSFP_2_RX3_N MGTFRXN3_126 66.1 11.3 BA45 QSFP_3_RX1_P MGTFRXP1_124 66.3 11.3 BA46...
  • Page 26 ADM-PCIE-9V8 User Manual Trace Delay Trace Length Signal Name Pin Name (ps) (mm) Number 112.4 19.2 QSFP_1_TX0_P MGTFTXP0_131 113.7 19.4 QSFP_1_TX6_N MGTFTXN2_130 113.8 19.4 QSFP_1_TX6_P MGTFTXP2_130 114.0 19.5 AH43 QSFP_2_RX6_P MGTFRXP2_127 114.2 19.5 AH44 QSFP_2_RX6_N MGTFRXN2_127 115.0 19.7 QSFP_0_TX4_P MGTFTXP0_133 115.0...
  • Page 27 ADM-PCIE-9V8 User Manual Trace Delay Trace Length Signal Name Pin Name (ps) (mm) Number 131.7 22.5 QSFP_1_RX2_N MGTFRXN2_131 132.9 22.7 AK39 QSFP_2_TX6_N MGTFTXN2_127 133.0 22.7 AM38 QSFP_2_TX4_P MGTFTXP0_127 133.0 22.7 AM39 QSFP_2_TX4_N MGTFTXN0_127 133.1 22.8 AK38 QSFP_2_TX6_P MGTFTXP2_127 136.0 23.2...
  • Page 28 ADM-PCIE-9V8 User Manual Trace Delay Trace Length Signal Name Pin Name (ps) (mm) Number 160.9 27.5 QSFP_0_TX1_P MGTFTXP1_132 161.5 27.6 BB43 QSFP_3_TX4_N MGTFTXN0_125 161.8 27.7 BB42 QSFP_3_TX4_P MGTFTXP0_125 166.2 28.4 QSFP_0_TX3_P MGTFTXP3_132 166.2 28.4 QSFP_0_TX3_N MGTFTXN3_132 166.7 28.5 AP43 QSFP_2_RX0_P MGTFRXP0_126 166.9...
  • Page 29 ADM-PCIE-9V8 User Manual Trace Delay Trace Length Signal Name Pin Name (ps) (mm) Number 669.4 114.4 FIREFLY_0_RX0_N MGTFRXN0_229 669.5 114.4 FIREFLY_3_RX3_P MGTFRXP3_226 669.6 114.5 FIREFLY_0_RX0_P MGTFRXP0_229 671.4 114.8 FIREFLY_1_RX2_P MGTFRXP2_228 671.5 114.8 FIREFLY_1_RX2_N MGTFRXN2_228 672.6 115.0 FIREFLY_3_RX1_N MGTFRXN1_226 672.7 115.0...
  • Page 30 ADM-PCIE-9V8 User Manual Trace Delay Trace Length Signal Name Pin Name (ps) (mm) Number 763.8 130.6 FIREFLY_0_TX1_N MGTFTXN1_229 765.1 130.8 FIREFLY_1_TX1_P MGTFTXP1_228 765.3 130.8 FIREFLY_1_TX1_N MGTFTXN1_228 768.6 131.4 FIREFLY_2_TX0_P MGTFTXP0_227 768.8 131.4 FIREFLY_2_TX0_N MGTFTXN0_227 770.0 131.6 FIREFLY_1_TX0_P MGTFTXP0_228 770.0 131.6...

  • Page 31: Appendix B Complete Pinout Table

    ADM-PCIE-9V8 User Manual Appendix B: Complete Pinout Table Signal Name Pin Name Bank Voltage Number BF23 AVR_B2U_1V8 IO_L2P_T0L_N2_66 1.8 (LVCMOS18) BA24 AVR_MON_CLK_1V8 IO_L12P_T1U_N10_GC_66 1.8 (LVCMOS18) BF22 AVR_U2B_1V8 IO_L2N_T0L_N3_66 1.8 (LVCMOS18) BF12 CCLK CCLK_0 1.8 (LVCMOS18) BA12 DONE_1V8 DONE_0 1.8 (LVCMOS18)
  • Page 32 ADM-PCIE-9V8 User Manual Signal Name Pin Name Bank Voltage Number FIREFLY_1_RX1_P MGTFRXP1_228 FIREFLY_1_RX2_N MGTFRXN2_228 FIREFLY_1_RX2_P MGTFRXP2_228 FIREFLY_1_RX3_N MGTFRXN3_228 FIREFLY_1_RX3_P MGTFRXP3_228 AY35 FIREFLY_1_SCL_1V8 IO_L17N_T2U_N9_AD10N_68 1.8 (LVCMOS18) AW35 FIREFLY_1_SDA_1V8 IO_L17P_T2U_N8_AD10P_68 1.8 (LVCMOS18) FIREFLY_1_TX0_N MGTFTXN0_228 FIREFLY_1_TX0_P MGTFTXP0_228 FIREFLY_1_TX1_N MGTFTXN1_228 FIREFLY_1_TX1_P MGTFTXP1_228 FIREFLY_1_TX2_N MGTFTXN2_228...
  • Page 33 ADM-PCIE-9V8 User Manual Signal Name Pin Name Bank Voltage Number AY33 FIREFLY_3_INT_1V8_L IO_L19N_T3L_N1_DBC_AD9N_68 1.8 (LVCMOS18) BE31 FIREFLY_3_MODPRS_L IO_L4N_T0U_N7_DBC_AD7N_68 1.8 (LVCMOS18) AV33 FIREFLY_3_RST_1V8_L IO_L20P_T3L_N2_AD1P_68 1.8 (LVCMOS18) FIREFLY_3_RX0_N MGTFRXN0_226 FIREFLY_3_RX0_P MGTFRXP0_226 FIREFLY_3_RX1_N MGTFRXN1_226 FIREFLY_3_RX1_P MGTFRXP1_226 FIREFLY_3_RX2_N MGTFRXN2_226 FIREFLY_3_RX2_P MGTFRXP2_226 FIREFLY_3_RX3_N MGTFRXN3_226 FIREFLY_3_RX3_P...
  • Page 34 ADM-PCIE-9V8 User Manual Signal Name Pin Name Bank Voltage Number AT18 FPGA_FLASH_DQ7 IO_L21N_T3L_N5_AD8N_D07_65 1.8 (LVCMOS18) AY31 GPIO_0_1V8_N IO_L14N_T2L_N3_GC_67 1.8 (LVCMOS18) AW30 GPIO_0_1V8_P IO_L14P_T2L_N2_GC_67 1.8 (LVCMOS18) AW31 GPIO_1_1V8_N IO_L15N_T2L_N5_AD11N_67 1.8 (LVCMOS18) AV31 GPIO_1_1V8_P IO_L15P_T2L_N4_AD11P_67 1.8 (LVCMOS18) AW29 GPIO_2_1V8_N IO_L16N_T2U_N7_QBC_AD3N_67 1.8 (LVCMOS18)
  • Page 35 ADM-PCIE-9V8 User Manual Signal Name Pin Name Bank Voltage Number PCIE_TX2_PIN_P MGTYTXP2_224 PCIE_TX3_PIN_N MGTYTXN3_224 PCIE_TX3_PIN_P MGTYTXP3_224 PCIE_TX4_PIN_N MGTYTXN0_225 PCIE_TX4_PIN_P MGTYTXP0_225 PCIE_TX5_PIN_N MGTYTXN1_225 PCIE_TX5_PIN_P MGTYTXP1_225 PCIE_TX6_PIN_N MGTYTXN2_225 PCIE_TX6_PIN_P MGTYTXP2_225 PCIE_TX7_PIN_N MGTYTXN3_225 PCIE_TX7_PIN_P MGTYTXP3_225 AT19 PERST0_1V8_L IO_T3U_N12_PERSTN0_65 1.8 (LVCMOS18) BB11 PROGRAM_B_1V8 PROGRAM_B_0 1.8 (LVCMOS18)
  • Page 36 ADM-PCIE-9V8 User Manual Signal Name Pin Name Bank Voltage Number QSFP_0_TX0_P MGTFTXP0_132 QSFP_0_TX1_N MGTFTXN1_132 QSFP_0_TX1_P MGTFTXP1_132 QSFP_0_TX2_N MGTFTXN2_132 QSFP_0_TX2_P MGTFTXP2_132 QSFP_0_TX3_N MGTFTXN3_132 QSFP_0_TX3_P MGTFTXP3_132 QSFP_0_TX4_N MGTFTXN0_133 QSFP_0_TX4_P MGTFTXP0_133 QSFP_0_TX5_N MGTFTXN1_133 QSFP_0_TX5_P MGTFTXP1_133 QSFP_0_TX6_N MGTFTXN2_133 QSFP_0_TX6_P MGTFTXP2_133 QSFP_0_TX7_N MGTFTXN3_133 QSFP_0_TX7_P MGTFTXP3_133...
  • Page 37 ADM-PCIE-9V8 User Manual Signal Name Pin Name Bank Voltage Number BF37 QSFP_1_SDA_1V8 IO_L7N_T1L_N1_QBC_AD13N_68 1.8 (LVCMOS18) QSFP_1_TX0_N MGTFTXN0_131 QSFP_1_TX0_P MGTFTXP0_131 QSFP_1_TX1_N MGTFTXN1_131 QSFP_1_TX1_P MGTFTXP1_131 QSFP_1_TX2_N MGTFTXN2_131 QSFP_1_TX2_P MGTFTXP2_131 QSFP_1_TX3_N MGTFTXN3_131 QSFP_1_TX3_P MGTFTXP3_131 QSFP_1_TX4_N MGTFTXN0_130 QSFP_1_TX4_P MGTFTXP0_130 QSFP_1_TX5_N MGTFTXN1_130 QSFP_1_TX5_P MGTFTXP1_130 QSFP_1_TX6_N...
  • Page 38 ADM-PCIE-9V8 User Manual Signal Name Pin Name Bank Voltage Number AG45 QSFP_2_RX7_P MGTFRXP3_127 BC36 QSFP_2_SCL_1V8 IO_L12P_T1U_N10_GC_68 1.8 (LVCMOS18) BD36 QSFP_2_SDA_1V8 IO_L12N_T1U_N11_GC_68 1.8 (LVCMOS18) AT39 QSFP_2_TX0_N MGTFTXN0_126 AT38 QSFP_2_TX0_P MGTFTXP0_126 AR41 QSFP_2_TX1_N MGTFTXN1_126 AR40 QSFP_2_TX1_P MGTFTXP1_126 AP39 QSFP_2_TX2_N MGTFTXN2_126 AP38 QSFP_2_TX2_P...
  • Page 39 ADM-PCIE-9V8 User Manual Signal Name Pin Name Bank Voltage Number AT43 QSFP_3_RX6_P MGTFRXP2_125 AR46 QSFP_3_RX7_N MGTFRXN3_125 AR45 QSFP_3_RX7_P MGTFRXP3_125 BD38 QSFP_3_SCL_1V8 IO_L9N_T1L_N5_AD12N_68 1.8 (LVCMOS18) BB37 QSFP_3_SDA_1V8 IO_L10P_T1U_N6_QBC_AD4P_68 1.8 (LVCMOS18) BF43 QSFP_3_TX0_N MGTFTXN0_124 BF42 QSFP_3_TX0_P MGTFTXP0_124 BE41 QSFP_3_TX1_N MGTFTXN1_124 BE40 QSFP_3_TX1_P...
  • Page 40 ADM-PCIE-9V8 User Manual Signal Name Pin Name Bank Voltage Number SI5328_0_CLKIN2_P MGTREFCLK1P_131 MGT REFCLK SI5328_0_CLKOUT1_PIN_N MGTREFCLK0N_133 MGT REFCLK SI5328_0_CLKOUT1_PIN_P MGTREFCLK0P_133 MGT REFCLK SI5328_0_CLKOUT2_PIN_N MGTREFCLK0N_131 MGT REFCLK SI5328_0_CLKOUT2_PIN_P MGTREFCLK0P_131 MGT REFCLK AR27 SI5328_0_RST_1V8_L IO_L24P_T3U_N10_67 1.8 (LVCMOS18) AU27 SI5328_1_1V8_INT_C1B IO_L20P_T3L_N2_AD1P_67 1.8 (LVCMOS18)

  • Page 41: Table 10 Complete Pinout Table

    ADM-PCIE-9V8 User Manual Signal Name Pin Name Bank Voltage Number BE13 TMS_0 1.8 (LVCMOS18) AU25 USER_LED_G0_1V8 IO_L16P_T2U_N6_QBC_AD3P_66 1.8 (LVCMOS18) AU24 USER_LED_G1_1V8 IO_L16N_T2U_N7_QBC_AD3N_66 1.8 (LVCMOS18) AV23 USER_LED_G2_1V8 IO_L17P_T2U_N8_AD10P_66 1.8 (LVCMOS18) AV22 USER_LED_G3_1V8 IO_L17N_T2U_N9_AD10N_66 1.8 (LVCMOS18) AU21 USER_LED_G4_1V8 IO_L18P_T2U_N10_AD2P_66 1.8 (LVCMOS18) AV21...
  • Page 42 ADM-PCIE-9V8 User Manual Revision History Date Revision Changed By Nature of Change Initial Release 12-Oct-2023 K. Roth Address: Suite L4A, 160 Dundee Street, Address: 10822 West Toller Drive, Suite 250 Edinburgh, EH11 1DQ, UK Littleton, CO 80127 Telephone: +44 131 558 2600...

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