Ddr4 Sdram; Mig Ip Setup Requirements For Rev 1 Pcbs; Mig Ip Setup Requirements Rev2 + Newer Pcbs - Alpha Data ADM-PCIE-8K5 User Manual

ADM-PCIE-8K5 User Manual

3.4 DDR4 SDRAM

Two banks of DDR4 SDRAM memory are soldered down to the board. While the factory default is 8GB/per bank,
16GB/bank is also supported through a build variant. Please see
interface is 72-bit wide data (64 data + 8 ECC). Maximum signaling rate is 2400 MT/s for 16GB total and
1688MT/s with 32GB total.
Memory solutions are available from the Xilinx Memory Interface Generator (MIG) and must use Vivado 2016.1
or later. An example project with traffic generator is available with purchase of the ADM-PCIE-8K5 SDK.
However, all the information required to generate a complete MIG IP core is available within this user guide.

3.4.1 MIG IP setup requirements for rev 1 PCBs

8GB per bank, rev1 PCB
• Vivado 2016.1 IP Catalog: DDR4 SDRAM (MIG)
• Memory Device Interface Speed (ps): 938
• Refernce Input Clock speed (ps): 3332
• Custom Parts Data File: Checked, use 'adm-pcie-8k5_custom_parts_2133.csv' downloaded from
www.alpha-data.com/8k5
• Configuration: Components
• Memory Part: CUSTOM_DBI_MT40A1G8PM-083E
• Data Mask and DBI: NO DM DBI WR RD
• IO locations found in appendix

3.4.2 MIG IP setup requirements rev2 + newer PCBs

8GB per bank, rev2 and newer PCB
• Vivado 2016.3 IP Catalog: DDR4 SDRAM (MIG)
• Memory Device Interface Speed (ps): 833
• Refernce Input Clock speed (ps): 3332
• Custom Parts Data File: Checked, use 'adm-pcie-'8k5_custom_parts_2400.csv' downloaded from
www.alpha-data.com/8k5
• Configuration: Components
• Memory Part: CUSTOM_DBI_MT40A1G8PM-083E
• Data Mask and DBI: NO DM DBI WR RD
• IO locations found in appendix
Functional Description
ad-ug-1319_v1_12.pdf
Order Code for all order options. The memory
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