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Alpha Data ADM-XRC-II Pro Hardware Manual

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ADM-XRC-II Pro
(ADM-XP)
Hardware Manual
ADM-XR-IIPro User Manual
Page 1 of 29
Version 0.2

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Summary of Contents for Alpha Data ADM-XRC-II Pro

  • Page 1 ADM-XRC-II Pro (ADM-XP) Hardware Manual ADM-XR-IIPro User Manual Page 1 of 29 Version 0.2...
  • Page 2 Email: support@alpha-data.com Copyright © 2002, 2003, 2004 Alpha Data Parallel Systems Ltd. All rights reserved. This publication is protected by Copyright Law, with all rights reserved. No part of this publication may be reproduced, in any shape or form, without prior written consent from Alpha Data Parallel Systems Limited.
  • Page 3 Revision History Revision Date Comments Jul-04 Initial 0.1+ DATA1, DATA8 DATA13 and DATA15 – polarity swapped DATA38 pin nos swapped in Manual Clock pins updated for XP pinouts (were XPL pinouts) Nov-04 Removed XRM-Pro Debug Section – added XRM ETH ADM-XR-IIPro User Manual Page 3 of 29 Version 0.2...

  • Page 4: Table Of Contents

    ADM-XP User Manual Contents INTRODUCTION ............................5 ............................5 PECIFICATIONS INSTALLATION ............................6 ....................... 6 OTHERBOARD REQUIREMENTS ........................6 ANDLING INSTRUCTIONS ADM-XP ................6 NSTALLING THE ONTO A MOTHERBOARD ADM-XP ADC-PMC ................6 NSTALLING THE IF FITTED TO AN HARDWARE OVERVIEW..........................7 LOCAL BUS ARCHITECTURE ........................

  • Page 5: Introduction

    PowerPC processors. The XP utilises an FPGA PCI bridge developed by Alpha Data supporting 64 bit PCI at up to 66MHz. Future enhancements will provide compatibility with PCI-X. A high speed multiplexed address and data bus connects the bridge to the target FPGA.

  • Page 6: Installation

    ADM-XP User Manual 2 Installation This chapter explains how to install the ADM-XP onto a PMC motherboard. Motherboard requirements The XP is a 3.3V only PCI device and is not compatible with systems that use 5V signalling. The XP must be installed in a PMC motherboard that supplies 3.3V power to the PMC connectors. Ensure that the motherboard satisfies this requirement before powering it up.

  • Page 7: Hardware Overview

    Flash Target User Flash Virtex II FG676 2V1500 Local Bus Virtex II Pro - FF1704 146 Bit 64/66 PCI PCIX 133 Alpha Data PCI/ 2VP70-2VP125 IO Bus Clocks PCIX to Local Bus Bridge MGT Bus Target Power Config DDR2 Flash...
  • Page 8 ADM-XP User Manual The physical layout is shown in the diagram below. The DDR DRAM and DDR2 SSRAM devices are clam shelled and appear on both sides of the board. 2V1500 Bridge Flash 2VP70-2VP100 Target Clock Flash Power U13 - Samtec DP Connector J5 - Jtag Header MGT's JP1 - VIO Selection...

  • Page 9: Local Bus Architecture

    ADM-XP User Manual 4 Local Bus Architecture The XP implements a multi-master local bus between the bridge and the target FPGA using a 32 or 64 multiplexed address and data path. The bridge design is asynchronous and allows the local bus to be run faster or slower than the PCI bus clock to suit the complexity of the user design.

  • Page 10: Target Fpga

    ADM-XP User Manual 5 Target FPGA The target FPGA is a V2PRO 2VP70, 2VP100 or 2VP125 (when available) in an FF1704 package. On the XP, all of the resources such as DDR, DDR2 SSRAM, IO and Flash are available no matter what device is fitted. The V2PRO has 8 banks of I/O and banks 0 and 1 provide the User IO to the front panel .
  • Page 11 ADM-XP User Manual within the V2Pro device and the allocation of the MGT resources on the board the MGT’s are currently limited to 2.5GBps operation using the REFCLK input to the transceivers. The MCLK signal is input to the FPGA to provide a user clock of between 10 and 200MHz, single ended. The local bus uses LCLK to synchronize transfers between the bridge and the target and is derived from MCLK by a divide by 2 in the ICS307.

  • Page 12: Sdram Ddr Memory

    ADM-XP User Manual 5.3 SDRAM DDR Memory The XP provides 2 independent banks of 64MB of DDR SDRAM with the option of 128MB when devices become available. Two Micron MT46V16M16 devices are fitted and are organised as 4Mx16x4. These devices can be operated at between 75MHz and 133MHz and depending on resource usage within the FPGA, a 2VP70 can easily achieve 100MHz (DDR200) operation.

  • Page 13: Ddr2 Ssram

    ADM-XP User Manual 5.4 DDR2 SSRAM The XP supports four independent banks of CIO DDR2 SSRAM memory. The devices fitted are Samsung 512K *36 (K7I163684-FC16) parts or a functional equivalent. As an upgrade option 1Mx36 (K7I323684-FC16) devices can also be fitted. DDR2 SSRAM Bank 0 DDR2 SSRAM Bank 2 Add0[0:21]...

  • Page 14: Flash Memory

    ADM-XP User Manual 5.5 Flash Memory The XP supports a flash device connected to the V2PRO for general purpose applications. Typically in applications that use a PPC core the flash is used to hold bootstrap or application code. The flash memory has its own set of pins located within banks 3 and 4 of the V2Pro and the IO voltage on the Flash device is set at 2.5V.

  • Page 15: Front Panel I/O

    ADM-XP User Manual 6 Front Panel I/O The XP supports standard XRM’s used on the ADM-XRC-II and ADM-XPL cards and also has an additional connector that brings 7 MGT channels upto the XRM Module site using a differential 28 pin Samtec QSE-DP series connector to maintain signal integrity.
  • Page 16 ADM-XP User Manual (Continued) FPGA Signal Connector Pins Signal FPGA IO_73N_1 IO_68N_1 IO_73P_1 IO_68P_1 IO_47N_1 IO_37N_1 IO_47P_1 IO_37P_1 IO_48N_1 IO_38N_1 IO_48P_1 IO_38P_1 IO_55N_1 IO_39P_1 IO_55P_1 IO_39N_1 IO_56P_1 IO_43N_1 IO_56N_1 IO_43P_1 IO_59N_1 IO_44P_1 IO_59P_1 IO_44N_1 IO_60N_1 IO_46N_1 IO_60P_1 IO_46P_1 IO_74P_1 IO_65N_1 IO_74N_1 IO_65P_1 IO_64P_1...

  • Page 17: Rocketio Multi-Gigabit Transceivers - U13

    ADM-XP User Manual 6.2 RocketIO Multi-Gigabit Transceivers – U13 The ADM-XP provides an additional connection upto the XRM module site which provides 7 MGT connection from the Virtex II pro device. This enables customisable Mulit Gigabit IO capability using XRM modules interfacing to the additional samtec QSE-DP connector.

  • Page 18: User Io - Pmc Pn4 (Rear Panel)

    ADM-XP User Manual 7 User IO – PMC PN4 (rear panel) User I/O is presented on the User Connector Pn4 via a standard 64-way PMC connector. This should be routed via a suitable CMC compliant motherboard to an external I/O adapter. FPGA Pin Signal Pn4 Pin...

  • Page 19: Jtag Access

    ADM-XP User Manual 8 JTAG Access The XP provides JTAG access for the fabric of the board through J6. This header will connect to Xilinx download cables using 3V3 signalling levels and has the following devices present in the scan chain :- hdr_TDO Target hdr_TDI...

  • Page 20: Xrm-Eth

    ADM-XP User Manual 9 XRM-ETH 9.1 Introduction The XRM-ETH is a general-purpose adaptor for the ADM-XPL and ADM-XRC-II series of PMC modules. It provides 10/100 Ethernet, RS-232 and general purpose I/O for use with a wide variety of IP. The XRM-ETH is supplied with two cables to enable connections from the XRM-ETH to 15 way PC COM ports and RJ45 Ethernet.

  • Page 21: 10/100 Ethernet

    ADM-XP User Manual 9.4 10/100 Ethernet The XRM-ETH Ethernet capability is supported by a Kendin KS8721B 2.5V PHY. This device is capable of auto-sensing 10 or 100Mb networks and has a standard MII interface suitable for connection to MAC IP in the FPGA.

  • Page 22: Input And Output Assignments (Adm-Xp)

    ADM-XP User Manual 9.5 Input and Output Assignments (ADM-XP) 9.5.1 Mictor I/O FPGA XRM-ETH Bank Samtec J2 Mictor Signal PAIR_1_P PAIR_1_N PAIR_2_P PAIR_2_N PAIR_3_P PAIR_3_N PAIR_4_P PAIR_4_N PAIR_5_P PAIR_5_N PAIR_6_P PAIR_6_N PAIR_7_P PAIR_7_N PAIR_8_P PAIR_8_N PAIR_9_P PAIR_9_N PAIR_10_P PAIR_10_N PAIR_11_P PAIR_11_N PAIR_12_P PAIR_12_N...

  • Page 23: Ethernet Mac

    ADM-XP User Manual 9.5.3 Ethernet MAC All of these signals use VCCFPIO signalling levels. The VCCO selected by the jumper on the XRC-II/XPL should match the IOSTANDARD for these pins. FPGA XRM-ETH Bank Samtec MAC Signal Comment O-ST O-ST TXER RXDV O-PD RXD3...

  • Page 24: User I/O Xrm Io146 Front Panel Variant - Rev2.0

    ADM-XP User Manual 10 User I/O XRM IO146 Front Panel Variant – Rev2.0 There are 146 I/O signals available on the front panel connector and these can be used individually or in pairs. All of these pins are compatible with 2.5V and 3.3V signaling (dependant on IO voltage setting on JP1). Care must be taken when using these signal pins not to exceed the maximum ratings for the V2PRO device.
  • Page 25 ADM-XP User Manual Function Term VII Pro Function Term VII Pro name name Data[0] +ve User[0] Data[1] -ve User[2] Data[0] –ve User[1] Data[1] +-ve User[3] Data[2] +ve User[4] Data[3] +ve User[6] Data[2] –ve User[5] Data[3] -ve User[7] Data[4] +ve User[8] Data[5] +ve User[10] Data[4] –ve...
  • Page 26 ADM-XP User Manual Function UCF name VII Pro Function UCF name VII Pro Data[48] +ve User[110] Data[49] +ve User[112] Data[48] -ve User[111] Data[49] -ve User[113] Data[50] +ve User[114] Data[51] +ve User[116] H34(5) Data[50] -ve User[115] G34(5) Data[51] -ve User[117] Data[52] +ve User[118] Data[53] +ve User[120]...

  • Page 27: User I/O Xrm Io146 - Rocket

    ADM-XP User Manual 11 User I/O XRM IO146 – Rocket The XRM-IO146 - Rocket is based on the XRM-IO146 module but has bank 4 on the mictor used to bring out the 7 MGT channels available on the ADM-XP boards. The termination scheme on the differential and single ended IO has also been changed from the standard XRM-IO146 allowing termination for LVPECL and BLVDS standards to be implemented on the XRM module rather than externally.
  • Page 28 ADM-XP User Manual Function Term VII Pro Function Term VII Pro name name Data[0]+ve User[0] Data[1]-ve User[2] Data[0]–ve User[1] Data[1]+ve User[3] Data[2]+ve User[4] Data[3]+ve User[6] Data[2]–ve User[5] Data[3]-ve User[7] Data[4]+ve User[8] Data[5]+ve User[10] Data[4]–ve User[9] Data[5]-ve User[11] Data[6]+ve User[12] Data[7]+ve User[14] Data[6]–ve User[13]...
  • Page 29 ADM-XP User Manual Function VII Pro Function VII Pro UCF name UCF name MGT_SYS_RXP22 BB35 MGT_SYS_TXP22 BB36 MGT_SYS_RXN22 BB34 MGT_SYS_TXN22 BB37 MGT_SYS_RXP11 MGT_SYS_TXP11 MGT_SYS_RXN11 MGT_SYS_TXN11 Single 5 Single 7 Single 4 Single 6 MGT_SYS_RXP10 MGT_SYS_TXP10 MGT_SYS_RXN10 MGT_SYS_TXN10 MGT_SYS_RXP15 MGT_SYS_TXP15 MGT_SYS_RXN15 MGT_SYS_TXN15 MGT_SYS_RXP14 MGT_SYS_TXP14...

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