Configuration; Configuration From Flash Memory; Building And Programming Configuration Images; Figure 13 Flash Address Map - Alpha Data ADM-PCIE-8K5 User Manual

3.10 Configuration

There are two main ways of configuring the FPGA on the ADM-PCIE-8K5:
• From Flash memory, at power-on, as described in
• Using USB cable connected at the front panel USB port

3.10.1 Configuration From Flash Memory

The FPGA can be automatically configured at power-on from a 1 Gbit BPI flash memory device (Micron part
number MT28GU01GAAA1EGC-0SIT). This Flash device is divided into two regions of 64 MiByte each, where
each region is sufficiently large to hold an uncompressed bitstream for a KU115 FPGA.
The ADM-PCIE-8K5 is shipped with a bitstream, corresponding to the "dma_demo" FPGA design from the
ADM-PCIE-8K5 SDK, programmed into region 1 and "reg_access" programmed into region 0. This permits basic
confidence and performance testing to be performed on a board without needing to program anything into the
Flash memory. Alpha Data recommends that region 0 is used as a fallback image; this permits relatively simple
recovery, without requiring direct programming of the FPGA over the front panel USB connection, in the event of
programming a "bad" bitstream into region 1.
The flash address map is as detailed below:
At power-on, the FPGA attempts to configure itself automatically in BPI mode from region 1 unless the
configuration header on the bitstream ultilizes multi-boot. Multibook and ICAP can be used to selected between
the two configuration regions to be loaded into the FPGA. See Xilinx UG570 MultiBoot for details.
The Lockdown function of the Flash device is controlled via switch SW1-2. When SW1-2 is OFF, any blocks in
the Flash whose Lockdown flag is set are write-protected. The factory default for the Lockdown flag of all Flash
blocks is clear, so that any block in the Flash can be written.

3.10.1.1 Building and Programming Configuration Images

Generate a bitfile with these constraints (see XAPP587):
• set_property BITSTREAM.GENERAL.COMPRESS {TRUE} [ current_design ]
• set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
• set_property BITSTREAM.CONFIG.BPI_SYNC_MODE {TYPE1} [current_design]
• set_property BITSTREAM.CONFIG.UNUSEDPIN {Pullnone} [current_design]
• set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
• set_property CONFIG_MODE {BPI16} [current_design]
• set_property CFGBVS GND [ current_design ]
• set_property CONFIG_VOLTAGE 1.8 [ current_design ]
Generate an MCS file with these properties (write_cfgmem):
• -format MCS
• -size 128
• -interface BPIx16
Page 18
Section 3.10.1
Section 3.10.2
Start Address (Bytes)
0x000_0000
Region 0
Failsafe
(64 MiB)
0x400_0000
Region 1
Default
(64 MiB)
Figure 13 : Flash Address Map
ADM-PCIE-8K5 User Manual
Functional Description
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