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Summary of Contents for Alpha Data ADM-XRC-II
- Page 1 ADM-XRC-II PCI Mezzanine Card User Guide Version 1.5...
- Page 2 ADM-XRC-II User Manual Copyright © 2002 Alpha Data Parallel Systems Ltd. All rights reserved. This publication is protected by Copyright Law, with all rights reserved. No part of this publication may be reproduced, in any shape or form, without prior written consent from Alpha Data Parallel Systems Limited.
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Page 3: Table Of Contents
Handling instructions ................. 2 2.3. Installing the ADM-XRC-II onto a PMC motherboard ......2 2.4. Installing the ADM-XRC-II if fitted to an ADC-PMC ......2 Board Overview ..................3 PCI Bus Interface..................4 ADM-XRC-II Local Bus Architecture ............5 5.1. - Page 4 ADM-XRC-II User Manual FPGA Pin Locations ................27 ADM-XRC-II User Manual Version 1.5...
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Page 5: Introduction
ADM-XRC-II User Manual Introduction The ADM-XRC-II is a high performance PCI Mezzanine Card (PMC) format device designed for supporting development of applications using the Virtex-II series of FPGA’s from Xilinx. SSRAM Interface 256K x 32/36 PLX 9656 SSRAM Target/ 256K x 32/36... -
Page 6: Installation
2.4. Installing the ADM-XRC-II if fitted to an ADC-PMC The ADM-XRC-II can be supplied for use in standard PC systems fitted to an ADC-PMC carrier board. The ADC-PMC can support up to two ADC-PMC cards whilst maintaining host PC PCI compatibility. If you are using a ADC- PMC64 refer to the supplied documentation for information on jumper settings. -
Page 7: Board Overview
ADM-XRC-II User Manual Board Overview The ADM-XRC-II PMC provides an easy way to achieve PCI performance without the need to develop or incorporate PCI cores into the FPGA design. The benefit provided by this architecture means faster development time and reduced cost in evaluating and testing FPGA applications. -
Page 8: Pci Bus Interface
The PCI bus is implemented in a PLX PCI9656 and is configured with settings as described later in this document to simplify the integration of user applications in the FPGA. The PCI configuration space of the ADM-XRC-II is shown below. Config. Offset... -
Page 9: Adm-Xrc-Ii Local Bus Architecture
ADM-XRC-II User Manual ADM-XRC-II Local Bus Architecture It is useful to refer to the PLX PCI9656 user manual for information on the operation of the local bus and how address spaces map to the BAR’s in PCI configuration space. The first two BAR’s decode memory and I/O ranges for the PCI9656 internal registers. -
Page 10: Local Control Registers
DONE. After configuration, the INIT pin becomes a user I/O pin and has no further function on the ADM-XRC-II. In this case the place and route program sets the INIT pin to an input with a weak pull down thus resulting in INIT appearing set. -
Page 11: Ccon Register
ADM-XRC-II User Manual 5.2.2. CCON Register The CCON register controls access to the ICS9161A clock generator. The range of frequencies supported is between 25 and 66 MHz. Although the XRC can operate at frequencies less than 25MHz, the CLKDLL circuits in the FPGA will not. -
Page 12: Icon Registers
ADM-XRC-II User Manual 5.2.3. ICON Registers The ICON registers consist of a mask register and an interrupt status register. The mask register can be set or cleared by writing to IMSET or IMCLR with a bit mask. The XRC only supports one interrupt from the local bus and is masked, set or cleared using bit 0. -
Page 13: Mode Register
ADM-XRC-II User Manual 5.2.5. MODE Register The MODE register contains fields that allow the additional functionality of operations to be specified. MODE BREV IMODE MODE BREV IMODE IMODE 0 => Edge triggered interrupt mode 1 => Level sensitive interrupt mode BREV 0 =>... -
Page 14: Input Clocks
ADM-XRC-II User Manual recommended that alterations to VCLK use REG1 or REG2 to set the new value so that on reset the VCLK output selects REG0 when S1/S0 are reset. PCI9656 CPLD Control Logic MCLK SRAM Virtex Clocks FPGA VCLK 14.3181... -
Page 15: Output Clocks
ADM-XRC-II User Manual VCLK is input to the FPGA on GCK1 (pin AF18) and can be used for any purpose within the FPGA. 5.5. Output Clocks The FPGA is responsible for providing clocks to the SRAM’s and also for aligning its internal global clock with the local bus clock. To do this requires the use of Virtex DCM’s that are specifically designed for the purpose of... -
Page 16: Local Bus
ADM-XRC-II User Manual 5.6. Local Bus The local bus of the ADM-XRC-II uses the PCI9656 to provide a non- multiplexed address and data capability with synchronous speeds of up to 66MHz, independent of PCI operation. Whilst the local bus is capable of achieving near PCI performance, it is much simpler to interface with than PCI. -
Page 17: Synchronous Sram
ADM-XRC-II User Manual 5.7. Synchronous SRAM The four banks of synchronous SRAM are identical in device type and FPGA interface. The devices fitted as pipelined ZBT parts organised as 256Kx32/36 bits each. The pins are allocated to support synchronous burst or ZBT SRAM and each bank provides the following interface. -
Page 18: User I/O Configuration
5.9. User I/O Configuration The ADM-XRC-II is fitted with and IO adapter to provide user I/O capability via the front panel. This allows many different IO connectors and standards to be easily supported. Currently the following IO adapter cards are available 5.9.1. -
Page 19: User I/O Xrm Io146 Panel Variant
ADM-XRC-II User Manual Signal Signal USER[0] USER[1] USER[2] USER[3] USER[4] USER[5] USER[6] USER[7] USER[8] USER[9] USER[10] USER[11] USER[12] USER[13] USER[14] USER[15] USER[16] USER[17] USER[18] USER[19] All GND USER[20] USER[21] USER[22] USER[23] USER[24] USER[25] USER[26] USER[27] USER[28] USER[29] USER[30] USER[31] USER[32] -CLK USER[33] -CLK 5.9.2. - Page 20 ADM-XRC-II User Manual Pin numbering looking into front of XRM IO146 connector Function Term V II Pin Function Term V II Pin name name Data[0] +ve User[0] Data[1] +ve User[2] Data[0] -ve User[1] Data[1] -ve User[3] Data[2] +ve User[4] Data[3] +ve...
- Page 21 ADM-XRC-II User Manual Function Term V II Pin Function Term V II Pin name name Data[32] +ve User[74] Data[33] +ve User[76] Data[32] -ve User[75] Data[33] -ve User[77 Data[34] +ve User[78] Data[35] +ve User[80] Data[34] -ve User[79] Data[35] -ve User[81] Data[36] +ve...
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Page 22: User I/O Pmc Pn4
ADM-XRC-II User Manual 5.10. User I/O PMC Pn4 User I/O is presented on the User Connector Pn4 via a standard 64-way PMC connector. This should be routed via a suitable CMC compliant motherboard to an external I/O adapter. Signal Pn4 Pin... -
Page 23: Configuring The Fpga
Xilinx. The driver for the ADM-XRC-II loads this file and determines the location of the binary bitstream data within it. This data is not suitable for writing directly to the Selectman registers as it is bit reversed. -
Page 24: Interrupts
ADM-XRC-II User Manual Interrupts The PCI9656 can provide a number of interrupts from internal sources as well as from the local bus. The FPGA can interrupt the host system by asserting the LINTIL (active low) signal and keeping it asserted until the source of the interrupt is cleared. -
Page 25: Flash Memory
28F128J3A and is paged into a 2 Mbyte region accessible on the Local Bus. Refer to section 5.2 for further information on the flash paging register The ADM-XRC-II is capable of loading the FPGA from flash on power up or reset and will load the bitstream from the main memory section starting at 0x8001. -
Page 26: Plx Pci9656 Initialisation
The PCI9656 is configured at power-up and reset by a serial EEPROM attached to it. This device is configured at the factory with settings to suit the standard operation of the ADM-XRC-II. For the values in the EEPROM, see the following chapter. -
Page 27: Local Configuration Registers
2. The Extra Long Load from Serial EEPROM bit indicates that the extended EEPROM load was performed. This is required to set up Space 1 and some other registers. 3. Expansion ROM Space is not implemented in the ADM-XRC-II and should not be altered. ADM-XRC-II User Manual Version 1.5... -
Page 28: Direct Master Pci Remap Register
9.2.7. Runtime Registers The runtime registers group together mailboxes, control and status registers. The only registers applicable to the ADM-XRC-II in this group are the INTCSR register at offset 68h and CNTRL at offset 6Ch. It should be noted that Mailbox 0 and 1 can be set to initial values using the EEPROM. -
Page 29: Eeprom, Pci, User Io
ADM-XRC-II User Manual 9.2.9. EEPROM, PCI, User IO This register is known as CNTRL and reports information about the state of the EEPROM interface, DMA transfer codes and general purpose input and output bits. Notes. 1. A fault with the EEPROM or if the EEPROM is blank will result in the Serial EEPROM Present bit being cleared. -
Page 30: Eeprom Contents
ADM-XRC-II User Manual EEPROM Contents There is a utility in the SDK that can be used to view and change the contents of the EEPROM. As this device contains PLX PCI9656 initialisation data users must be careful about the changes made. - Page 31 ADM-XRC-II User Manual FPGA Pin Locations Refer to the SDK which contains UCF files for various local bus, SRAM and IO configurations. ADM-XRC-II User Manual Version 1.5 Page 27...
- Page 32 ADM-XRC-II User Manual Revision History Date Revision Nature of Change July-2001 Initial draft Nov-2001 Updates I/O modules Flash Page Info PLX Configuration register info SRAM Clocking Dec-2001 Updates XRM IO146 Rev 2.0 added Feb-2002 Updates I/O UCF / FPGA pin cross reference...
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