Ddr4 Sdram Reference Clocks; Pci Express; Table; Table 10 Firefly Reference Clocks - Alpha Data ADM-PCIE-8K5 User Manual

SI5328_REFCLK_OUT1
PCIE_REFCLK_1
GTH_CLK_2

3.2.6 DDR4 SDRAM Reference Clocks

The two banks of DDR4 SDRAM memory each require a separate reference clock, as per Xilinx UltraScale MIG
design guidelines. The reference clocks for these interfaces are detailed below:
Both clocks are 300MHz by default.
MEM_CLK_0
MEM_CLK_1

3.3 PCI Express

The ADM-PCIE-8K5 is capable of PCIe Gen 1/2/3 with 1/2/4/8 lanes. The FPGA drives these lanes directly using
the Integrated PCI Express block from Xilinx. Negotiation of PCIe link speed and number of lanes used is
generally automatic and does not require user intervention.
PCI Express reset (PERST#) connected to the FPGA at both pins AE15 and AM15.
The other pin assignments for the high speed lanes are provided in the pinout attached to the

Table

Note:
Different motherboards/backplanes will benefit from different RX equalization schemes within the PCIe IP core
provided by Xilinx. Alpha Data recommends using the following setting if a user experiences link errors or
training issues with their system: within the IP core generator, change the mode to "Advanced" and open the
"GT Settings" tab, change the "form factor driven insertion loss adjustment" from "Add-in Card" to
"Chip-to-Chip" (See Xilinx PG239 for more details).
Page 10
Signal Target FPGA Input
MGTREFCLK0_231
MGTREFCLK1_231
MGTREFCLK0_232
EXT_CLK MGTREFCLK1_232
Table 10 : FireFly Reference Clocks
Signal Target FPGA Input
IO_L11_T1U_GC_66
IO_L11_T1U_GC_44
Table 11 : Memory Reference Clocks
ADM-PCIE-8K5 User Manual
I/O Standard "P" pin
LVDS K10
LVDS H10
LVDS F10
User D10
I/O Standard "P" pin
DIFF_HSTL_I_12
G16
(or SSTL)
DIFF_HSTL_I_12
AM22
(or SSTL)
"N" pin
K9
H9
F9
D9
"N" pin
G15
AN22
Complete Pinout
Functional Description
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