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Alpha Data ADM-PCIE-8K5 User Manual

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ADM-PCIE-8K5
User Manual
Document Revision: 1.12
17th July 2023

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Summary of Contents for Alpha Data ADM-PCIE-8K5

  • Page 1 ADM-PCIE-8K5 User Manual Document Revision: 1.12 17th July 2023...
  • Page 2 ADM-PCIE-8K5 User Manual © 2023 Copyright Alpha Data Parallel Systems Ltd. All rights reserved. This publication is protected by Copyright Law, with all rights reserved. No part of this publication may be reproduced, in any shape or form, without prior written consent from Alpha Data Parallel Systems Ltd.

  • Page 3: Table Of Contents

    ADM-PCIE-8K5 User Manual Table Of Contents Introduction ............................1 Key Features ..........................1 Order Code ............................ 1 PCB Information ..........................2 Physical Specifications ......................... 2 Chassis Requirements ........................2 2.2.1 PCI Express ..........................2 2.2.2 Mechanical Requirements ......................2 2.2.3 Power Requirements .........................
  • Page 4 Table 14 Status LED Definitions ........................16 Table 15 Complete Pinout Table ........................23 List of Figures Figure 1 ADM-PCIE-8K5 Product Photo ......................1 Figure 2 Thermal Performance ........................4 Figure 3 Thermal Performance ........................4 Figure 4 ADM-PCIE-8K5 Block Diagram ......................5 Figure 5 Switches .............................

  • Page 5: Introduction

    ADM-PCIE-8K5 User Manual 1 Introduction The ADM-PCIE-8K5 is a high-performance reconfigurable computing card intended for Data Center applications, featuring a Xilinx Kintex UltraScale FPGA. Figure 1 : ADM-PCIE-8K5 Product Photo 1.1 Key Features Key Features • PCIe Gen1/2/3 x1/2/4/8 capable •...

  • Page 6: Pcb Information

    The PCIe Specification permits a standard low-profile, half-length PCIe card to dissipate up to 25 W of power, drawn from the PCIe slot. The ADM-PCIE-8K5 may consume more than 25 W of power for larger user FPGA designs. Power estimation requires the use of the Xilinx XPE spreadsheet and/or a power estimator tool available from Alpha Data.

  • Page 7: Table 3 Available Power By Rail

    ADM-PCIE-8K5 User Manual Voltage Source Name Current Capability 0.95 VCC_INT + VCCINT_IO + VCC_BRAM VCCAUX + VCCAUX_IO VCCO_1.8V VCCO_3.3V VCCO_1.2V MGTVCCAUX MGTAVCC MGTAVTT Table 3 : Available Power By Rail PCB Information Page 3 ad-ug-1319_v1_12.pdf...

  • Page 8: Thermal Performance

    2.3 Thermal Performance The ADM-PCIE-8K5 comes with a heat sink to reduce the heat of the FPGA which is typically the hottest point on the card. The FPGA die temperature must remain under 100 degrees Celsius or the system monitor will clear the FPGA design to ensure the card does not overheat.

  • Page 9: Functional Description

    3 Functional Description 3.1 Overview The ADM-PCIE-8K5 is a versatile reconfigurable computing platform with a Kintex UltraScale KU115-2E FPGA, Gen3x8 PCIe interface, two banks of DDR4 both 72 bits wide (for 64 bits with 8 bits ECC), two SFP+ cages capable of up to 16.375Gbps each and any Xilinx supported standard (Ethernet, SRIO, Infiniband, SDI, etc.), two...

  • Page 10: Switches

    ADM-PCIE-8K5 User Manual 3.1.1 Switches The ADM-PCIE-8K5 has a quad DIP switch SW1, located on the rear side of the board. The function of each switch in SW1 is detailed below: Figure 5 : Switches Factory Switch Function OFF State...

  • Page 11: Leds

    ADM-PCIE-8K5 User Manual 3.1.2 LEDs There are 6 LEDs on the ADM-PCIE-8K5, 3 of which are general purpose and whose meaning can be defined by the user. The other four have fixed functions described below: USR_LED_G0 USR_LED_R USER_LED_G1 STAT_0 STAT_1...

  • Page 12: Clocking

    ADM-PCIE-8K5 User Manual 3.2 Clocking The ADM-PCIE-8K5 provides reference clocks for the DDR4 SDRAM banks and the I/O interfaces available to the user. After a clock is programmed to a certain frequency, that frequency will become the default on power-up.

  • Page 13: Sfp

    400MHz by re-programing the Si5338 reprogrammable clock oscillator via system monitor. This can be done using the Alpha Data API or over USB with the appropriate Alpha Data Software tools. Any changes made to the default clock frequency are non-volatile and will be used moving forward.

  • Page 14: Ddr4 Sdram Reference Clocks

    Table 11 : Memory Reference Clocks 3.3 PCI Express The ADM-PCIE-8K5 is capable of PCIe Gen 1/2/3 with 1/2/4/8 lanes. The FPGA drives these lanes directly using the Integrated PCI Express block from Xilinx. Negotiation of PCIe link speed and number of lanes used is generally automatic and does not require user intervention.

  • Page 15: Ddr4 Sdram

    Memory solutions are available from the Xilinx Memory Interface Generator (MIG) and must use Vivado 2016.1 or later. An example project with traffic generator is available with purchase of the ADM-PCIE-8K5 SDK. However, all the information required to generate a complete MIG IP core is available within this user guide.

  • Page 16: Sfp

    ADM-PCIE-8K5 User Manual 3.5 SFP+ Two SFP+ cages are available at the front panel. Both cages are capable of housing either active optical or passive copper SFP compatible components. The communication interface can run at up to 16.375Gbps per channel. These cages are ideally suited for 10 Gigabit Ethernet or any other protocol supported by the Xilinx GTH Transceivers.

  • Page 17: Firefly

    8 lanes at 16.375Gps resulting in 131Gbps total bandwidth. This can be configured in a ring orientation as depicted in the image below, or allow for MPO style breakouts at the front panel (full-height panel only).The ADM-PCIE-8K5 support both copper and optical FireFly modules. More information on FireFly can be found at https://www.samtec.com/optics/optical-cable/mid-board/firefly Both FireFly sites have control signals connected to the FPGA.

  • Page 18: Table 12 Firefly Part Numbers

    ADM-PCIE-8K5 User Manual The FireFly modules are broken out to the front panel as shown in the image below. The Samtec FireFly optical module ties the PCB to the front panel where an industry standard MPO coupler is used for attachment to external cabling.

  • Page 19: System Monitor

    ADM-PCIE-8K5 User Manual 3.7 System Monitor The ADM-PCIE-8K5 monitors temperature, voltage, and current of the board to check on the operation of the board. The monitoring is implemented using an Atmel AVR microcontroller. All readings and measurements are available to the FPGA, enabling detailed power consumption reporting.

  • Page 20: System Monitor Status Leds

    ADM-PCIE-8K5 User Manual 3.7.2 System Monitor Status LEDs LEDs D6 (Red) and D5 (Green) indicate the card health status. LEDs Status Green Running and no alarms Green + Red Standby (Powered off) Flashing Green + Flashing Red Attention - critical alarm active...

  • Page 21: Sma Timing Input

    ADM-PCIE-8K5 utilizes the Digilent USB-JTAG converter box which is supported by the Xilinx software tool suite. Simply connect a micro-USB AB type cable between the ADM-PCIE-8K5 USB port and a host computer with Vivado installed. Vivado Hardware Manager will automatically recognize the FPGA and allow you to configure the FPGA and the BPI configuration PROM.

  • Page 22: Configuration

    Flash memory. Alpha Data recommends that region 0 is used as a fallback image; this permits relatively simple recovery, without requiring direct programming of the FPGA over the front panel USB connection, in the event of programming a "bad"...

  • Page 23: Custom Flash Write Interface

    3.10.1.2 Custom Flash Write Interface Alpha Data's reference design bridge allows users to write images to the BPI configuration flash over the PCIE interface. Other customers may want similar functionality built into their own IP. In order to enable this...

  • Page 24: Gpio

    ADM-PCIE-8K5 User Manual 3.11 GPIO The ADM-PCIE-8K5 has a GPIO feature. This feature is partially fit by default, and if serial transceivers are required it must be specified in the part number. See Order Code for more details on ordering options.

  • Page 25: User Eeprom

    ADM-PCIE-8K5 User Manual 3.12 User EEPROM A 2Kb I2C user EEPROM is provided for storing MAC addresses or other user information. The EEPROM is part number M24C02-RMC6TG. The address pins A2, A1, and A0 are all strapped to a logical '0'.
  • Page 26 ADM-PCIE-8K5 User Manual Page Intentionally left blank Page 22 Functional Description ad-ug-1319_v1_12.pdf...

  • Page 27: Appendix A: Complete Pinout Table

    ADM-PCIE-8K5 User Manual Appendix A: Complete Pinout Table Signal Name Bank Voltage Number 1V8_DIG INPUT AT18 AVR_B2U AU16 AVR_HS_B2U AU17 AVR_HS_CLK AV19 AVR_HS_U2B AW18 AVR_MON_CLK AT17 AVR_U2B AC11 CCLK DDR4_0_A0 DDR4_0_A1 DDR4_0_A10 DDR4_0_A11 DDR4_0_A12 DDR4_0_A13 DDR4_0_A14 DDR4_0_A15 DDR4_0_A16 DDR4_0_A17 DDR4_0_A2...
  • Page 28 ADM-PCIE-8K5 User Manual Signal Name Bank Voltage Number DDR4_0_C1 DDR4_0_C2 DDR4_0_CK_C DDR4_0_CK_T DDR4_0_CKE DDR4_0_CS_N DDR4_0_DM0 DDR4_0_DM1 DDR4_0_DM2 DDR4_0_DM3 DDR4_0_DM4 DDR4_0_DM5 DDR4_0_DM6 DDR4_0_DM7 DDR4_0_DM8 DDR4_0_DQ0 DDR4_0_DQ1 DDR4_0_DQ10 DDR4_0_DQ11 DDR4_0_DQ12 DDR4_0_DQ13 DDR4_0_DQ14 DDR4_0_DQ15 DDR4_0_DQ16 DDR4_0_DQ17 DDR4_0_DQ18 DDR4_0_DQ19 DDR4_0_DQ2 DDR4_0_DQ20 DDR4_0_DQ21 DDR4_0_DQ22 DDR4_0_DQ23...
  • Page 29 ADM-PCIE-8K5 User Manual Signal Name Bank Voltage Number DDR4_0_DQ28 DDR4_0_DQ29 DDR4_0_DQ3 DDR4_0_DQ30 DDR4_0_DQ31 DDR4_0_DQ32 DDR4_0_DQ33 DDR4_0_DQ34 DDR4_0_DQ35 DDR4_0_DQ36 DDR4_0_DQ37 DDR4_0_DQ38 DDR4_0_DQ39 DDR4_0_DQ4 DDR4_0_DQ40 DDR4_0_DQ41 DDR4_0_DQ42 DDR4_0_DQ43 DDR4_0_DQ44 DDR4_0_DQ45 DDR4_0_DQ46 DDR4_0_DQ47 DDR4_0_DQ48 DDR4_0_DQ49 DDR4_0_DQ5 DDR4_0_DQ50 DDR4_0_DQ51 DDR4_0_DQ52 DDR4_0_DQ53 DDR4_0_DQ54 DDR4_0_DQ55 DDR4_0_DQ56...
  • Page 30 ADM-PCIE-8K5 User Manual Signal Name Bank Voltage Number DDR4_0_DQ60 DDR4_0_DQ61 DDR4_0_DQ62 DDR4_0_DQ63 DDR4_0_DQ64 DDR4_0_DQ65 DDR4_0_DQ66 DDR4_0_DQ67 DDR4_0_DQ68 DDR4_0_DQ69 DDR4_0_DQ7 DDR4_0_DQ70 DDR4_0_DQ71 DDR4_0_DQ8 DDR4_0_DQ9 DDR4_0_DQS0_C DDR4_0_DQS0_T DDR4_0_DQS1_C DDR4_0_DQS1_T DDR4_0_DQS2_C DDR4_0_DQS2_T DDR4_0_DQS3_C DDR4_0_DQS3_T DDR4_0_DQS4_C DDR4_0_DQS4_T DDR4_0_DQS5_C DDR4_0_DQS5_T DDR4_0_DQS6_C DDR4_0_DQS6_T DDR4_0_DQS7_C DDR4_0_DQS7_T DDR4_0_DQS8_C...
  • Page 31 ADM-PCIE-8K5 User Manual Signal Name Bank Voltage Number DDR4_0_TEN AG22 DDR4_1_A0 AE20 DDR4_1_A1 AH23 DDR4_1_A10 AH22 DDR4_1_A11 AF23 DDR4_1_A12 AF22 DDR4_1_A13 AK23 DDR4_1_A14 AE21 DDR4_1_A15 AL22 DDR4_1_A16 AF20 DDR4_1_A17 AL20 DDR4_1_A2 AJ23 DDR4_1_A3 AK21 DDR4_1_A4 AM20 DDR4_1_A5 AN21 DDR4_1_A6 AD21...
  • Page 32 ADM-PCIE-8K5 User Manual Signal Name Bank Voltage Number AR26 DDR4_1_DM4 DDR4_1_DM5 DDR4_1_DM6 DDR4_1_DM7 DDR4_1_DM8 AV23 DDR4_1_DQ0 AT22 DDR4_1_DQ1 AR28 DDR4_1_DQ10 AW25 DDR4_1_DQ11 AU27 DDR4_1_DQ12 AV26 DDR4_1_DQ13 AT28 DDR4_1_DQ14 AW26 DDR4_1_DQ15 AL28 DDR4_1_DQ16 AJ25 DDR4_1_DQ17 AH26 DDR4_1_DQ18 AH24 DDR4_1_DQ19 AT24 DDR4_1_DQ2...
  • Page 33 ADM-PCIE-8K5 User Manual Signal Name Bank Voltage Number AN26 DDR4_1_DQ37 AM25 DDR4_1_DQ38 AP28 DDR4_1_DQ39 AW23 DDR4_1_DQ4 DDR4_1_DQ40 DDR4_1_DQ41 DDR4_1_DQ42 DDR4_1_DQ43 DDR4_1_DQ44 DDR4_1_DQ45 DDR4_1_DQ46 DDR4_1_DQ47 DDR4_1_DQ48 DDR4_1_DQ49 AU22 DDR4_1_DQ5 DDR4_1_DQ50 DDR4_1_DQ51 DDR4_1_DQ52 DDR4_1_DQ53 DDR4_1_DQ54 DDR4_1_DQ55 DDR4_1_DQ56 DDR4_1_DQ57 DDR4_1_DQ58 DDR4_1_DQ59 AW21 DDR4_1_DQ6...
  • Page 34 ADM-PCIE-8K5 User Manual Signal Name Bank Voltage Number AV21 DDR4_1_DQ7 DDR4_1_DQ70 DDR4_1_DQ71 AT27 DDR4_1_DQ8 AV27 DDR4_1_DQ9 AV22 DDR4_1_DQS0_C AU21 DDR4_1_DQS0_T AU26 DDR4_1_DQS1_C AU25 DDR4_1_DQS1_T AL25 DDR4_1_DQS2_C AL24 DDR4_1_DQS2_T AG24 DDR4_1_DQS3_C AF24 DDR4_1_DQS3_T AR25 DDR4_1_DQS4_C AP25 DDR4_1_DQS4_T DDR4_1_DQS5_C DDR4_1_DQS5_T DDR4_1_DQS6_C DDR4_1_DQS6_T...
  • Page 35 ADM-PCIE-8K5 User Manual Signal Name Bank Voltage Number AK33 AJ33 AL17 FIREFLY0_INT_L AH17 FIREFLY0_MODPRS_L AL18 FIREFLY0_RESET_L FIREFLY0_RX0_N FIREFLY0_RX0_P FIREFLY0_RX1_N FIREFLY0_RX1_P FIREFLY0_RX2_N FIREFLY0_RX2_P FIREFLY0_RX3_N FIREFLY0_RX3_P AP19 FIREFLY0_SCL AK18 FIREFLY0_SDA AK17 FIREFLY0_SEL_L FIREFLY0_TX0_N FIREFLY0_TX0_P FIREFLY0_TX1_N FIREFLY0_TX1_P FIREFLY0_TX2_N FIREFLY0_TX2_P FIREFLY0_TX3_N FIREFLY0_TX3_P AM17 FIREFLY1_INT_L...
  • Page 36 ADM-PCIE-8K5 User Manual Signal Name Bank Voltage Number AH16 FIREFLY1_SDA AN16 FIREFLY1_SEL_L FIREFLY1_TX0_N FIREFLY1_TX0_P FIREFLY1_TX1_N FIREFLY1_TX1_P FIREFLY1_TX2_N FIREFLY1_TX2_P FIREFLY1_TX3_N FIREFLY1_TX3_P AJ15 FLASH_A0 AK15 FLASH_A1 AN13 FLASH_A10 AN12 FLASH_A11 AP14 FLASH_A12 AP13 FLASH_A13 AR12 FLASH_A14 AT12 FLASH_A15 AP15 FLASH_A16 AR15 FLASH_A17...
  • Page 37 ADM-PCIE-8K5 User Manual Signal Name Bank Voltage Number AL15 FLASH_ADV_L FLASH_CE_L AE11 FLASH_DQ0 AD10 FLASH_DQ1 AG12 FLASH_DQ10 AH12 FLASH_DQ11 AK13 FLASH_DQ12 AK12 FLASH_DQ13 AH13 FLASH_DQ14 AJ13 FLASH_DQ15 FLASH_DQ2 FLASH_DQ3 AF14 FLASH_DQ4 AG14 FLASH_DQ5 AE13 FLASH_DQ6 AF13 FLASH_DQ7 AF15 FLASH_DQ8 AG15...
  • Page 38 ADM-PCIE-8K5 User Manual Signal Name Bank Voltage Number MEM_CLK_0_PIN_P 1.2 (External Term Provided) AN22 MEM_CLK_1_PIN_N 1.2 (External Term Provided) AM22 MEM_CLK_1_PIN_P 1.2 (External Term Provided) MODE_0/2 MODE_0/2 AE12 ONBRD_CLK_1V8 AF12 ONBRD_DATA_1V8 PCIE_REFCLK_1_PIN_N MGT_CLK PCIE_REFCLK_1_PIN_P MGT_CLK PCIE_REFCLK_2_PIN_N MGT_CLK AT10 PCIE_REFCLK_2_PIN_P MGT_CLK...
  • Page 39 ADM-PCIE-8K5 User Manual Signal Name Bank Voltage Number PCIE_TX4_PIN_P PCIE_TX5_PIN_N PCIE_TX5_PIN_P PCIE_TX6_PIN_N PCIE_TX6_PIN_P PCIE_TX7_PIN_N PCIE_TX7_PIN_P AE15 PERST_1V8_0_L AM15 PERST_1V8_1_L AU31 POWER9_SCL_1V8 AV31 POWER9_SDA_1V8 AL30 PPS_BUF_1V8 PROGRAM_B_1V8 PUDC_B AH28 AH29 AH32 RXEN_L SFP+_RX0_N SFP+_RX0_P SFP+_RX1_N SFP+_RX1_P SFP+_TX0_N SFP+_TX0_P SFP+_TX1_N SFP+_TX1_P AM16...
  • Page 40 ADM-PCIE-8K5 User Manual Signal Name Bank Voltage Number AE17 SFP+1_RS1 AE18 SFP+1_SCL AF18 SFP+1_SDA AF19 SFP+1_TX_DISABLE AG19 SFP+1_TX_FAULT AU30 SI5328_1V8_SCL AU29 SI5328_1V8_SDA AN32 SI5328_REFCLK_IN_N AM32 SI5328_REFCLK_IN_P SI5328_REFCLK_OUT0_PIN_N MGT_CLK SI5328_REFCLK_OUT0_PIN_P MGT_CLK SI5328_REFCLK_OUT1_PIN_N MGT_CLK SI5328_REFCLK_OUT1_PIN_P MGT_CLK AR20 SPARE_SCL AT20 SPARE_SDA AP16 SPARE_WP...

  • Page 41: Revision History

    ADM-PCIE-8K5 User Manual Revision History Date Revision Changed By Nature of Change Initial Draft 25 Feb 2016 K. Roth Initial Release, updated Fabric Clock to CMOS, updated 29 Mar 2016 K. Roth photos, updated SDK reference. Updated DDR4 SDRAM to specify DDR4-2133 as maximum...
  • Page 42 ADM-PCIE-8K5 User Manual Date Revision Changed By Nature of Change Updated USB Front Panel Interface to include clock indexes 24 Oct 2019 1.11 K. Roth Updated USB Front Panel Interface to correct download 14 Jan 2022 1.12 K. Roth links.