Sfp; Firefly; Table 8 Emcclk; Table 9 Sfp+ Reference Clocks - Alpha Data ADM-PCIE-8K5 User Manual

ADM-PCIE-8K5 User Manual
REFCLK100M

3.2.4 SFP+

The SFP+ cages are located in MGT tiles 227 and 228 and use two unique clock sources. Both clocks are
initially set to 156.25MHz. Note that these clock frequency can be changed to any arbitrary clock frequency up to
400MHz by re-programing the Si5338 reprogrammable clock oscillator via system monitor. This can be done
using the Alpha Data API or over USB with the appropriate Alpha Data Software tools. Any changes made to the
default clock frequency are non-volatile and will be used moving forward.
GTH_CLK_0
GTH_CLK_1
SI5328_REFCLK_OUT0
The SFP+ cages are also located such that they can be clocked from a Si5328 jitter attenuator clock multiplier. If
jitter attenuation is required please see the reference documentation for the Si5328. https://www.silabs.com/
Support%20Documents/TechnicalDocs/Si5328.pdf
The Si5328 is configured with a 114.285MHz oscilator on XA and XB, SDA and SCL pins can be found in the
Complete Pinout Table
The Si5328 input clock comes from FPGA pins found in the
SI5328_REFCLK_IN_P/N, and includes 100 Ohm AC coupled termination on the 1.8V FPGA bank.
The Jitter Attenuator is not fitted on rev3 and earlier (serial number less than 1300)

3.2.5 FireFly

The two FireFly sites are located in MGT tile 231 and 232 and can use a variety of reference clocks.
PCIE_REFCLK_1 is a buffered version of the PCIe edge clock. It is converted to LVDS through a NB6L11S clock
buffer.
GTH_CLK_2 is default to 156.25MHz. Note that these clock frequency can be changed to any arbitrary clock
frequency up to 400MHz by re-programing the Si5338 reprogrammable clock oscillator via system monitor. This
can be done using the Alpha Data API or over USB with the appropriate Alpha Data Software tools. Any changes
made to the default clock frequency are non-volatile and will be used moving forward.
EXT_CLK comes from the GPIO header. The signal is fed directly to the GTH clock with only 10nF capacitors in
series. Take care to supply a safe clock in on these signals. See Xilinx UG576 for more details acceptable on
GTH reference clocks.
SI5328_REFCLK_OUT1 comes from the onboard jitter attenuator which can feedback a recovered clock from
the GTH channel for particular standards. The Jitter Attenuator is not fitted by default and requires a custom bulid
option. Contact sales@alpha-data.com for more details.
Functional Description
ad-ug-1319_v1_12.pdf
Signal
IO_L24P_T3U_N10_EMCCLK_65
Signal Target FPGA Input
MGTREFCLK0_227
MGTREFCLK0_228
MGTREFCLK1_228
Table 9 : SFP+ Reference Clocks
at net names SI5328_1V8_SCL and SI5328_1V8_SDA (external pull-ups included).
Target FPGA Input
Table 8 : EMCCLK
I/O Standard
Complete Pinout Table
I/O Standard
LVCMOS18
"P" pin
LVDS AE8
LVDS AA8
LVDS W8
at net names
pin
AJ28
"N" pin
AE7
AA7
W7
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