Usb Interface; Configuration; Configuration From Flash Memory - Alpha Data ADM-PCIE-9V8 User Manual

ADM-PCIE-9V8 User Manual

3.7 USB Interface

The FPGA can be configured directly from the USB connection on either the front panel or the rear card edge.
The ADM-PCIE-9V8 utilizes the Digilent USB-JTAG converter box which is supported by the AMD software tool
suite. Simply connect a micro-USB AB type cable between the ADM-PCIE-9V8 USB port and a host computer
with Vivado installed. Vivado Hardware Manager will automatically recognize the FPGA and allow you to
configure the FPGA and the SPI configuration Flash memory.
The same USB connector is used to directly access the system monitor system. All voltages, currents,
temperatures, and non-volatile clock configuration settings can be accessed using Alpha Data's avr2util software
at this interface.
Avr2util for Windows and the associated USB driver is downloadable here:
https://support.alpha-data.com/pub/firmware/utilities/windows/
Avr2util for Linux is downloadable here:
https://support.alpha-data.com/pub/firmware/utilities/linux/
Use "avr2util.exe /?" to see all options.
For example "avr2util.exe /usbcom com4 display-sensors" will display all sensor values.
Change 'com4' to match the com port number assigned under windows device manager.

3.8 Configuration

There are two main ways of configuring the FPGA on the ADM-PCIE-9V8:
• From Flash memory, at power-on, as described in
• Using USB cable connected at either USB port

3.8.1 Configuration From Flash Memory

The FPGA can be automatically configured at power-on from two 1 Gbit QSPI flash memory device configured as
an x8 SPI device (Micron part numbers MT25QU01GBBB8E12-0). These flash devices are typically divided into
two regions of 128 MiByte each, where each region is sufficiently large to hold an uncompressed bitstream for a
VU2P FPGA.
The ADM-PCIE-9V8 is shipped with a simple PCIe endpoint bitstream which should be visible to the operating
system (using e.g. Windows Device Manager or "lspci" in Linux) in order to provided confidence that the card is
working correctly when installed in a system. On request, Alpha Data can pre-load custom bitstreams during
production test. Please contact sales@alpha-data.com in order to discuss this possibility.
It is possible to use Multiboot with a fallback image on this hardware. The master SPI configuration interface and
the Fallback MultiBoot are discussed in detail in Xilinx UG570.
At power-on, the FPGA attempts to configure itself automatically in SPI master mode, depending on the header
of the bitstream that has been flashed into the card. This normally results in SPIx8 configuration at EMCCLK
frequency. The configuration scheme used in the ADM-PCIE-9V5 is compatible with Multiboot; see Xilinx UG570
for details. The FPGA can also be made to reconfigure itself from an arbitrary Flash address using the ICAPE3
primitive; this is also described in Xilinx UG570.
The image loaded can also support tandem PROM or tandem PCIE with field update configuration methods.
These options reduce power-on load times to help meet the PCIe reset timing requirements. Tandem with field
also enables a host system to reconfigure the user FPGA logic without losing the PCIe link, a useful feature when
system resets and power cycles are not an option.
The Alpha Data System Monitor is also capable of reconfiguring the flash memory and reprograming the FPGA.
This provides a useful failsafe mechanism to re-program the FPGA even if it drops off the PCIe bus. The system
monitor can be accessed with avr2util over USB at the front panel and rear edge.
Functional Description
ad-ug-1467_v1_0.pdf
Section 3.8.1
Section 3.8.2
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