Ethernet; Xadc; Uart Configuration - Enclustra Mars AX3 User Manual

Parameter
Baud rate
Data
Parity
Stop
Flow control
Table 3: UART Configuration
2.1.9

Ethernet

The Ethernet MAC in the block design is connected to a Microchip (Micrel) KSZ9031 Ethernet PHY on the
Mars AX3 FPGA module using RGMII interface. The PHY can be configured via the MDIO management
interface on PHY address 3.
Note that without Tri-Mode Ethernet MAC and Tri-Mode Ethernet MAC Controller licenses (Permanent
or Evaluation), the FPGA bitstream generation will not be permitted. Therefore, Enclustra also provides
reference designs for all Mars AX3 FPGA module variants without Ethernet support.
An Ethernet Application Note is available as well providing sample code and more details about using
the Ethernet on Enclustra hardware [9].
Please note that the RGMII delays in the Ethernet PHY need to be configured according to the Mars AX3
FPGA module User Manual [3] when the Ethernet interface can be used.
Note that the Mars AX3 FPGA module has one Gigabit Ethernet PHY that uses the MDIO interface. The
PHY can be configured by using the corresponding address: 3
2.1.10

XADC

A Xilinx XADC IP core instance is connected to the Microblaze CPU via an AXI bus, in order to monitor
the temperature of the device. The temperature threshold for the FPGA is configured to its maximum
allowed temperature.
The constraints provided in the reference design enable FPGA bitstream power-down, when the temper-
ature increases above the threshold.
Depending on the user application, the Mars AX3 FPGA module may consume more power than can
be dissipated without additional cooling measures; always make sure the FPGA is adequately cooled by
installing a heat sink and/or providing air flow. Temperature control and monitoring is very important in
a complex design.
Information that may assist in selecting a suitable heat sink for the Mars AX3 FPGA module can be found
in the Enclustra Modules Heat Sink Application Note [10].
D-0000-492-002
Value
115'200
8 bit
None
1 bit
None
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