Fpga Bitstream Generation; Hardware Setup Step-By-Step Guide - Enclustra Mars AX3 User Manual

Step Description
6 Download and install Enclustra FX3 driver from the Enclustra download page [5].
Open a terminal program on your computer (e.g. Tera Term) and open a serial port connection
using the newly detected COM port labeled with the higher number of the detected ports.
For issues related to COM ports detection, refer to Section 5.4.
Configure the UART parameters according to Section 2.1.8.
Table 4: Hardware Setup Step-By-Step Guide
3.3

FPGA Bitstream Generation

For a fast test of the HelloWorld example application, the pre-generated bitstream may alternatively be
used, therefore the steps described in this section may be skipped.
A pre-generated bitstream for any AX3 variant is released on the AX3 Reference Design Github page.
Step Description
1 Configure the settings file:
1. Edit the module_name variable in scripts/settings.tcl file, according to your modules
name.
This file includes module name and board information required for the project creation
script. All settings, except for module_name should be left on default. The list of options
for module_name is given in the comments within the Tcl file.
2. Save the file after editing.
2 Start Xilinx Vivado 2022.1 and create the Mars AX3 FPGA module reference design project:
1. Click on the Tcl console at the bottom of the page and type:
(a) cd {<base_dir>}
where <base_dir> is the directory in which you extracted the archive contents.
Note the {} around the path.
(b) source ./scripts/create_project.tcl
2. Wait for completion
3 Run Synthesis, Implementation & Bitstream Generation in Vivado 2022.1:
1. Click on Generate Bitstream from the Flow Navigator bar
2. In the Launch Runs window click OK - this will start automatically the entire implemen-
tation process
3. Wait for completion
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Version 2022.1_v1.0.2, 04.01.2023