Gpios; I2C; Microblaze Debug Module (Mdm); Spi Controller - Enclustra Mars AX3 User Manual

The DDR settings in the MIG IP core must be configured according to the Mars AX3 FPGA module User
Manual [3].
2.1.4

GPIOs

A Xilinx GPIO controller is connected to the Microblaze processor via an AXI bus. Some FPGA GPIOs are
connected to LEDs in the top level, as described in Table 2.
The FPGA firmware contains a 24-bit counter freely running at 50 MHz. The MSB of this counter is used
to blink FPGA_LED0# with a frequency of approximately 3 Hz.
FPGA Pin Signal
M16 LED0#
M17 LED1#
L18 LED2#
M18 LED3#
Table 2: FPGA Firmware I/O Configuration
2.1.5

I2C

For available devices on the I2C bus refer to the Mars AX3 FPGA Module and Mars PM3 Base Board User
Manual [3] [4]. An I2C Application Note is available as well providing sample code and more details about
using I2C on Enclustra hardware [8].
2.1.6

Microblaze Debug Module (MDM)

A Microblaze Debug Module (MDM) is connected to the AXI bus, providing JTAG UART for base boards
that do not have a UART connection.
In order to use the MDM block, stdin and stdout must be configured to "JTAG UART" in the board support
package (Vitis) and JTAG UART must be selected in the Run Configuration window.
2.1.7

SPI Controller

The SPI controller is connected to the QSPI flash on the Mars AX3 FPGA module. Please refer to the Mars
AX3 FPGA Module User Manual [3] for details about flash programming and usage.
As the QSPI flash is connected to the configuration pins and the clock pin is not accessible as normal
user I/O pin, the SPI controller requires the "STARTUPE2" primitive to drive the clock, and the SPI clock
needs to be assigned to high impedance in the top-level HDL file.
The clock connection is done in Vivado by selecting the "Enable STARTUPE2 Primitive" checkbox from
the SPI controller settings within the block design.
2.1.8

UART

The UART is configured as shown in Table 3.
D-0000-492-002
Function
Blinking LED counter MSB
GPIO 1, controlled by the FPGA GPIO controller
GPIO 2, controlled by the FPGA controller
GPIO 2, controlled by the FPGA controller
6 / 24 Version 2022.1_v1.0.2, 04.01.2023