User Manuals: Enclustra Mercury Plus XU9 MPSoC Module

Manuals and User Guides for Enclustra Mercury Plus XU9 MPSoC Module. We have 1 Enclustra Mercury Plus XU9 MPSoC Module manual available for free PDF download: User Manual

Enclustra Mercury Plus XU9 User Manual

Enclustra Mercury Plus XU9 User Manual (61 pages)

SoC Module

Brand: Enclustra | Category: Computer Hardware | Size: 3 MB

Table of Contents

Table of Contents

3
- Rohs
  6
- Safety Recommendations and Warnings
  6
- Disposal and WEEE
  6
- Overview
  6
- Warranty
  6
- Introduction
  6
- General
  6
- Electromagnetic Compatibility
  7
- Features
  7
- Electrostatic Discharge
  7
- Deliverables
  8
- Accessories
  8
- Reference Design
  8
- Enclustra Build Environment
  8
- Petalinux BSP
  8
- Mercury+ ST1 Base Board
  9
- Enclustra Heat Sink
  9
- Mercury+ PE3 Base Board
  9
- Mercury+ PE1 Base Board
  9
- Xilinx Tool Support
  10
- Module Description
  11
- Block Diagram
  11
- Hardware Block Diagram
  11
- Standard Module Configurations
  12
- EN-Numbers and Part Names
  12
- Product Model Fields
  12
- Module Configuration and Product Models
  12
- Module Label
  13
- Numbers and Part Names
  13
- Top and Bottom Views
  14
- Top View
  14
- Bottom View
  14
- Module Top View
  14
- Module Bottom View
  14
- Top and Bottom Assembly Drawings
  15
- Top Assembly Drawing
  15
- Bottom Assembly Drawing
  15
- Module Top Assembly Drawing
  15
- Module Bottom Assembly Drawing
  15
- Module Footprint
  16
- Module Footprint - Top View
  16
- Module Connector Types
  17
- Mechanical Data
  17
- Module Connector
  17
- Pin Numbering for the Module Connector
  18
- User I/O
  18
- Pinout
  18
- I/O Pin Exceptions
  19
- User I/Os
  19
- I/O Pin Exceptions - PERST
  20
- I/O Pin Exceptions - Level Shifters
  20
- Differential I/Os
  21
- I/O Banks
  21
- I/O Banks
  22
- VCC_IO Usage
  22
- Signal Terminations
  23
- Multiplexed I/O (MIO) Pins
  24
- MIO Pins Connections Overview
  24
- Analog Inputs
  25
- Multi-Gigabit Transceiver (MGT)
  25
- System Monitor (PL) Parameters
  25
- MGT Pairs
  26
- Power
  27
- Power Generation Overview
  28
- Generated Power Supplies
  28
- Module Power Status and Control Pins
  29
- Power Enable/Power Good
  29
- Voltage Supply Inputs
  29
- Voltage Supply Outputs
  30
- Power Consumption
  30
- Heat Dissipation
  30
- Voltage Monitoring
  31
- Heat Sink Type
  31
- Voltage Monitoring Outputs
  31
- Module Clock Resources
  32
- Reset
  32
- Clock Generation
  32
- Leds
  33
- Ddr4 Sdram (Ps)
  33
- Reset Resources
  33
- User Leds
  33
- Status Leds
  33
- Parameters
  34
- DDR4 SDRAM (PS) Types
  34
- Signal Description
  34
- Termination
  34
- DDR4 SDRAM Type
  34
- Ddr4 Sdram (Pl)
  35
- DDR4 SDRAM (PS) Parameters
  35
- DDR4 SDRAM Type
  36
- Signal Description
  36
- Termination
  36
- Parameters
  36
- DDR4 SDRAM (PL) Types
  36
- DDR4 SDRAM (PL) Parameters
  37
- QSPI Flash
  37
- Signal Description
  37
- QSPI Flash Type
  37
- Configuration
  38
- QSPI Flash Corruption Risk
  38
- Emmc Flash
  38
- Emmc Flash Type
  38
- Gigabit Ethernet Phys Type
  39
- Ethernet PHY Type
  39
- Dual Gigabit Ethernet
  39
- SD Card
  39
- Signal Description
  39
- External Connectivity
  40
- MDIO Address
  40
- PHY Configuration
  40
- USB1/ETH1 Selection
  40
- Gigabit Ethernet Phys Configuration - RGMII Delays
  41
- Gigabit Ethernet Phys Configuration - Bootstraps
  41
- USB PHY Type
  41
- Usb 2.0
  41
- RGMII Delays Configuration
  41
- Signal Description
  42
- Usb 3.0
  42
- USB 2.0 PHY Type
  42
- Display Port
  43
- Real-Time Clock (RTC)
  43
- USB 3.0 Implementation Example
  43
- Secure EEPROM
  44
- EEPROM Type
  44
- Mpsoc Configuration Pins
  45
- Configuration Signals
  45
- Device Configuration
  45
- Module Connector C Detection
  46
- Pull-Up During Configuration
  46
- Pull-Up During Configuration (PUDC) and Power-On Reset Delay Override (PORSEL)
  46
- VCC_IO Pins
  46
- Power-On Reset Delay Override
  47
- Boot Mode
  47
- Jtag
  48
- JTAG on Module Connector
  48
- Boot Modes
  48
- JTAG Interface - PL and PS Access and Debug
  49
- JTAG Boot Mode
  49
- External Connectivity
  49
- JTAG Boot Mode Resistor - Assembly Drawing Top View (Lower Right Part)
  49
- Emmc Boot Mode
  50
- QSPI Boot Mode
  50
- SD Card Boot Mode
  50
- Emmc Flash Programming
  50
- QSPI Flash Programming Via JTAG
  50
- SD Card Boot Modes
  50
- QSPI Flash Programming from an External SPI Master - Signal Diagrams
  51
- QSPI Flash Programming from an External SPI Master
  51
- Enclustra Module Configuration Tool
  51
- Overview
  52
- Signal Description
  52
- I2C Address Map
  52
- I2C Signal Description
  52
- I2C Communication
  52
- Secure EEPROM
  53
- Memory Map
  53
- I2C Addresses
  53
- EEPROM Sector 0 Memory Map
  53
- Mpsoc Device Types
  54
- Product Information
  54
- Module Configuration
  54
- Module Temperature Range
  55
- Operating Conditions
  56
- Absolute Maximum Ratings
  56
- Recommended Operating Conditions
  57
- Ordering and Support
  58
- Ordering
  58
- Support
  58
List of Figures

59

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