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Enclustra Mars ZX2 User Manual

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Mars ZX2 SoC Module
Reference Design for Mars ST3 Base Board
Purpose
The purpose of this document is to present to the user the overall view of the Mars ZX2 SoC module
reference design and to provide the user with a step-by-step guide to the complete Xilinx® SoC design
flow used for the Mars ZX2 SoC module.
Summary
This document first gives an overview of the Mars ZX2 SoC module reference design and then guides
through the complete Xilinx SoC design flow for the Mars ZX2 SoC module in the getting started sec-
tion. In addition, the internals and the boot options of the Mars ZX2 SoC module reference design are
described.
Product Information
Product
Document Information
Reference / Version / Date
Approval Information
Written by
Verified by
Approved by
User Manual
Code
MA-ZX2
Reference
D-0000-489-003
Name
DDUE/ARUD/ESOM
GKOE
IJOS
Enclustra GmbH – Räffelstrasse 28 – CH-8045 Zürich – Switzerland
Name
Mars ZX2 SoC Module
Version
2022.1_v2.0.1
Position
Design Engineer
Design Expert
Manager, BU SP
Phone +41 43 343 39 43 – www.enclustra.com
Date
15.10.2022
Date
30.09.2022
05.10.2022
15.10.2022

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Summary of Contents for Enclustra Mars ZX2

  • Page 1 User Manual Purpose The purpose of this document is to present to the user the overall view of the Mars ZX2 SoC module reference design and to provide the user with a step-by-step guide to the complete Xilinx® SoC design flow used for the Mars ZX2 SoC module.
  • Page 2 License Copyright 2023 by Enclustra GmbH, Switzerland. Permission is hereby granted, free of charge, to any person obtaining a copy of this hardware, software, firmware, and associated documentation files (the ”Product”), to deal in the Product without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or...

  • Page 3: Table Of Contents

    Table of Contents Overview Introduction ..........Prerequisites .

  • Page 4: Overview

    Vivado Design Suite User Guide, Embedded Processor Hardware Design [1] Zynq®7000 All Programmable SoC Embedded Design Tutorial [2] More information on the Mars ZX2 SoC module and the Mars ST3 base board can be retrieved from their respective user manuals [3] [4].

  • Page 5: Reference Design Description

    The DDR3L SDRAM memory runs at its corresponding maximum PS DDR frequency at a voltage of 1.35 V by default. The clock frequency for the controller can be modified in the Zynq system. The DDR settings in the Zynq system must be configured according to the Mars ZX2 SoC Module User Manual [3].

  • Page 6: Sd Card

    The I2C controller I2C0 is configured to the 14..15 pins. The I2C1 controller is configured to the EMIOs. For available devices on the I2C bus refer to the Mars ZX2 SoC Module and Mars ST3 Base Board User Manual [3] [4]. An I2C Application Note is available as well providing sample code and more details about using I2C on Enclustra hardware [8].

  • Page 7: Ethernet

    The Ethernet MAC ENET 0 is mapped to MIO 16..27 and MIO 52..53 pins and is connected to the Microchip (Micrel) KSZ9031 Ethernet PHY on the Mars ZX2 SoC module using an RGMII interface. The PHY can be configured via the MDIO management interface on PHY address 3. Please note that the RGMII delays in the Ethernet PHY need to be configured before the Ethernet interface can be used.

  • Page 8: Programmable Logic (Pl)

    Temperature control and monitoring is very important in a complex design. Information that may assist in selecting a suitable heat sink for the Mars ZX2 SoC module can be found in the Enclustra Modules Heat Sink Application Note [10].

  • Page 9: Getting Started

    Warning! Never mount or remove the Mars ZX2 SoC module to or from the Mars ST3 base board while the Mars ST3 base board is powered. Always remove or turn off the power supply before mounting or removing the Mars ZX2 SoC module.

  • Page 10: Hardware Setup

    Set VCC_IO voltage to 2.5 V by configuring the DIP switch on the Mars ST3 base board as follows (see in Figure 2): CFG = [1: OFF, 2: OFF, 3: ON, 4: OFF] Mount the Mars ZX2 SoC module to the Mars ST3 base board. Continued on next page... D-0000-489-003 10 / 25...

  • Page 11: Fpga Bitstream Generation

    Figure 2). Make sure that the FTDI device on the Mars ST3 base board is configured to Xilinx JTAG mode using Enclustra MCT [5]. 1. Make sure no other FTDI devices are connected to the computer. To ensure, please use the FTprog utility [6] to enumerate all FTDI devices attached.

  • Page 12: Vitis Workspace Preparation

    Tcl file. 2. Save the file after editing. Start Xilinx Vivado 2022.1 and create the Mars ZX2 SoC module reference design project: 1. Click on the Tcl console at the bottom of the page and type: (a) cd {<base_dir>/reference_design}...

  • Page 13: Vitis Workspace Preparation Step-By-Step Guide

    Step Description Create a new Platform Project 1. File Platform Project 2. In the New Platform Project: (a) For Project Name type the <project_name> e.g. Mars_ZX2_ST3 (b) Hit Next (c) Select ”Create a new platform from hardware (XSA)” (d) Hit the Browse button and select the Hardware Specification .xsa file you exported from Vivado, as described in Section 3.3.

  • Page 14: Running Software Applications

    Running Software Applications This section describes how to run software applications on the Mars ZX2 SoC module. The steps are generic, and apply to the software example templates in the Vitis IDE. Step Description Create a run configuration for the application in Vitis IDE 2022.1: 1.

  • Page 15: Run Configurations Settings - Application Tab

    Figure 3: Run Configurations Settings - Application Tab Figure 4: Run Configurations Settings - Target Setup Tab D-0000-489-003 15 / 25 Version 2022.1_v2.0.1, 15.10.2022...

  • Page 16: Boot Configurations

    For a fast test of the boot configurations, the pre-generated .bin images may be used for boot, instead of rebuilding the image. You need to select the file corresponding to the Mars ZX2 SoC module variant. Pre-generated binaries for any ZX2 variant are released on the ZX2 Reference Design Github page.

  • Page 17: Programming The Qspi Flash

    4.1.2 Programming the QSPI Flash In order to program Zynq-7000 devices a modification to the standard FSBL generated during platform creation is needed. The created FSBL is limited to only running the initialization (ps7_init()). For more details on this please refer to the answer record by Xilinx AR70548. Step Description Modify the created Platform project...
  • Page 18 Add Configuration Memory Device (see Figure 7) (a) For Select Configuration Memory Part choose the memory part according to the Mars ZX2 SoC Module User Manual [3], part type single. This is in most cases s25fl512s-1.8v-qspi-x4-single. (b) Hit OK 4. In Program Configuration Memory Device window (see Figure 8): (a) For Configuration file select the boot image generated as described in Section 4.0.1...

  • Page 19: Enable Xilffs In Vitis

    Step Description Optional - alternatively, Enclustra Module Configuration Tool (MCT) [5] can be used to pro- gram the QSPI flash. The procedure implies setting another boot mode than QSPI during flash programming, so that the SoC does not try to boot while the flash is being programmed. The other boot mode in this case is SD card boot.

  • Page 20: Qspi Flash Programming Settings In Vitis

    Figure 6: QSPI Flash Programming Settings in Vitis Figure 7: QSPI Flash Programming Settings in Vivado - Adding the Memory Device D-0000-489-003 20 / 25 Version 2022.1_v2.0.1, 15.10.2022...

  • Page 21: Booting From The Qspi Flash

    Figure 8: QSPI Flash Programming Settings in Vivado Warning! Some Vivado and Vitis tool versions are reporting problems when configuring certain SoC devices or when using particular boot modes. Please try different tool versions and check the Xilinx documenta- tion and forums for help on the reported issue. 4.1.3 Booting from the QSPI Flash Step...

  • Page 22: Preparing The Hardware

    4.2.2 Preparing the Hardware Step Description Remove the power supply from the Mars ST3 base board (see label 12 V DC in Figure 2). Enable the SD card boot mode by setting the configuration DIP switches on the Mars ST3 base board as follows (see labels in Figure 2): CFG = [1: OFF, 2: OFF, 3: ON, 4: OFF]...

  • Page 23: Troubleshooting

    2. If built-in JTAG is used, check that the FTDI device is configured to Xilinx JTAG mode. This can be done using the Enclustra MCT software [5]. More information on the Xilinx JTAG mode configuration on the Mars ST3 base board can be retrieved from the Mars ST3 base board user manual [4].

  • Page 24: Qspi Boot Issues

    3. If the UART used is mapped to the EMIO pins in the PS, resetting the ARM core will not suffice. Reprogramming the PL is necessary, as the UART lines go through PL. 4. Make sure that Enclustra MCT software is not open. After closing it, unplug and plug in again the USB cable corresponding to the UART communication.
  • Page 25 [1] Vivado Design Suite User Guide, Embedded Processor Hardware Design, UG898, Xilinx, 2019 [2] Zynq-7000 All Programmable SoC Embedded Design Tutorial, UG1165, Xilinx, 2015 [3] Mars ZX2 SoC Module User Manual Ask Enclustra for details [4] Mars ST3 Base Board User Manual...

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