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Mercury+ XU6 SoC Module
Purpose
The purpose of this document is to present the characteristics of Mercury+ XU6 SoC module to the user,
and to provide the user with a comprehensive guide to understanding and using the Mercury+ XU6 SoC
module.
Summary
This document first gives an overview of the Mercury+ XU6 SoC module followed by a detailed description
of its features and configuration options. In addition, references to other useful documents are included.
Product Information
Product
Document Information
Reference / Version / Date
Approval Information
Written by
Verified by
Approved by
User Manual
Code
ME‐XU6
Reference
D‐0000‐464‐001
Name
RLOC
HMEY
IJOS
Enclustra GmbH – Räffelstrasse 28 – CH‐8045 Zürich – Switzerland
Name
Mercury+ XU6 SoC Module
Version
03
Position
Design Engineer
Design Expert
Manager, BU‐SP
Phone +41 43 343 39 43 – www.enclustra.com
Date
24.10.2023
Date
23.11.2020
05.10.2023
24.10.2023
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Chapters
Table of Contents
Related Manuals for Enclustra Mercury+ XU6
Summary of Contents for Enclustra Mercury+ XU6
- Page 1 Mercury+ XU6 SoC Module User Manual Purpose The purpose of this document is to present the characteristics of Mercury+ XU6 SoC module to the user, and to provide the user with a comprehensive guide to understanding and using the Mercury+ XU6 SoC module.
- Page 2 Unauthorized duplication of this document, in whole or in part, by any means is prohibited without the prior written permission of Enclustra GmbH, Switzerland. Although Enclustra GmbH believes that the information included in this publication is correct as of the date of publication, Enclustra GmbH reserves the right to make changes at any time without notice.
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Page 3: Table Of Contents
1.3.2 Enclustra Build Environment ........ - Page 4 ..... . . 49 3.12 Enclustra Module Configuration Tool ....... . . 50...
- Page 5 Operating Conditions Absolute Maximum Ratings ........55 Recommended Operating Conditions .
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Page 6: Overview
The Enclustra Build Environment [16] is available for the Mercury+ XU6 SoC module. This build system allows the user to quickly set up and run Linux on any Enclustra SoC module. It allows the user to choose the desired target and download all the required binaries, such as bitstream and FSBL ﴾First Stage Boot Loader﴿. -
Page 7: Safety Recommendations And Warnings
1.1.7 Electromagnetic Compatibility The Mercury+ XU6 SoC module is a Class A product ﴾as defined in IEC 61000‐3‐2 standard﴿ and is not intended for use in domestic environments. The product may cause electromagnetic interference, for which appropriate measures must be taken. -
Page 8: Deliverables
Enclustra Build Environment The Enclustra Build Environment ﴾EBE﴿ [16] enables the user to quickly set up and run Linux on any En‐ clustra SoC module or system board. It allows the user to choose the desired target, and download all the required binaries, such as bitstream and FSBL. -
Page 9: Petalinux Bsp
1.3.3 Petalinux BSP The Enclustra Petalinux BSPs enable the user to quickly set up a Petalinux project and to run Linux on the Enclustra SoC module or system board. The documentation [18] describes the build process in detail and allows a user without Petalinux knowl‐... -
Page 10: Module Description
Block Diagram Figure 1: Hardware Block Diagram The main component of the Mercury+ XU6 SoC module is the Xilinx Zynq UltraScale+ MPSoC device. Most of its I/O pins are connected to the Mercury+ module connector, making up to 254 regular user I/Os available to the user. -
Page 11: Module Configuration And Product Models
Table describes the available standard module configurations. The product model indicates the module type and main features. Figure describes the fields within the product model. Custom configurations are available. Contact Enclustra for more information. Product Model MPSoC DDR4 ﴾PS﴿ DDR4 ﴾PS﴿... -
Page 12: En-Numbers And Product Models
Figure 2: Product Model Fields For the first revision modules or early access modules, the product model may not respect entirely this naming convention. Contact Enclustra for more information. EN‐Numbers and Product Models Every product is uniquely labeled, showing the EN‐number and serial number. An example is presented in Figure 3. -
Page 13: Numbers And Product Models
EN‐Number Product Model Revision Number EN105296 ME‐XU6‐5EV‐2I‐D12E R2.0 EN105295 ME‐XU6‐4EV‐1I‐D13E R2.0 EN105294 ME‐XU6‐4EV‐1I‐D12E R2.0 EN105293 ME‐XU6‐4EV‐1I‐D12 R2.0 EN105292 ME‐XU6‐4CG‐1E‐D13 R2.0 EN105291 ME‐XU6‐4CG‐1E‐D12 R2.0 EN105290 ME‐XU6‐3EG‐2I‐D11 R2.0 EN105289 ME‐XU6‐2EG‐1I‐D13E R2.0 EN105287 ME‐XU6‐2CG‐1E‐D10H R2.0 EN105263 ME‐XU6‐4CG‐1E‐D13 R1.1 EN104543 ME‐XU6‐4EV‐1I‐D13E R1.1 EN104483 ME‐XU6‐4EV‐1I‐D12E R1.1 EN104385 ME‐XU6‐5EV‐2I‐D12E... -
Page 14: Top And Bottom Views
Top and Bottom Views Depending on the hardware revision and configuration, the module may look slightly different than shown in this document. 2.4.1 Top View Figure 4: Module Top View 2.4.2 Bottom View Figure 5: Module Bottom View D‐0000‐464‐001 14 / Version 03, 24.10.2023... -
Page 15: Top And Bottom Assembly Drawings
Top and Bottom Assembly Drawings Depending on the hardware revision and configuration, the module may look slightly different than shown in this document. 2.5.1 Top Assembly Drawing C1621 R1413 R1414 L1601 R1411 R1412 L1602 C1622 R1405 R1618 U301 R1416 R1619 C1626 R1209 R1410... -
Page 16: Module Footprint And Mechanical Data
Enclustra offers Mercury and Mercury+ modules of various geometries having widths of 56, 64, 65, 72 or 74 mm and having different topologies for the mounting holes. If different module types shall be fixed on the base board by screws, additional mounting holes may be required to accommodate different modules. -
Page 17: Module Connector
Ensure that the mounting holes on the base board are aligned with the mounting holes of the Mercury+ XU6 SoC module. Table describes the mechanical characteristics of the Mercury+ XU6 SoC module. A 3D model ﴾PDF﴿ and a STEP 3D model are available [8], [9]. Parameter... -
Page 18: User I/O
2.8.1 Pinout Information on the Mercury+ XU6 SoC module pins can be found in the Enclustra Mercury Master Pinout [11], and in the additional document Enclustra Module Pin Connection Guidelines [10]. The pin types on the schematic of the module connector and in the Master Pinout document are for reference only. -
Page 19: Mapping Between The Generic I/O Bank Letters And The Device-Specific I/O Bank Numbers
For example, IO_B66_L4_AD7_G3_P is located on pin G3 of I/O bank 66, pair 4, it is a System Monitor differential auxiliary analog input capable pin and it has positive polarity, when used in a differential pair. The HD banks are numbered differently depending on the MPSoC device assembled on the module. Ta‐ presents the mapping between the generic bank letters and the device‐specific bank numbers. -
Page 20: I/O Pin Exceptions
Signal Name Sign. Pairs Differential Single‐ I/O Bank I/O Bank ended Type IO_B64_<...> In/Out In/Out 4 signals are routed via level shifters ﴾Refer to Section 2.8.2 details﴿ IO_B65_<...> In/Out In/Out IO_B66_<...> In/Out In/Out IO_BE_<...> In/Out ﴾no LVDS/LVPECL outputs In/Out supported; internal differential termination not supported﴿... -
Page 21: I/O Pin Exceptions - Perst
Table 7: I/O Pin Exceptions ‐ PERST# When the Mercury+ XU6 SoC module is used in combination with a Mercury+ PE1 base board as a PCIe device, the PERST# signal coming from the PCIe edge connector on the module connector pin A104 ﴾PS_MIO42_PERST#﴿... -
Page 22: Differential I/Os
The information regarding the length of the signal lines from the MPSoC device to the module connector is available in Mercury+ XU6 SoC Module IO Net Length Excel Sheet [3]. This enables the user to match the total length of the differential pairs on the base board if required by the application. -
Page 23: Vcc_Io Usage
﴾Table 5﴿. Details on connectivity in I/O banks described by generic bank letters are presented in Section 2.8.4. For compatibility with other Enclustra Mercury modules, it is recommended to use a single I/O voltage per module connector. - Page 24 Signal Name MPSoC Pins Supported Connector Connector Connector Voltages A Pins B Pins C Pins VCC_CFG_MIO VCCO_PSIO1_501, 1.8 V ‐ 3.3 V A74, A77 ‐ ‐ VCCO_PSIO3_503, VCCO_BE VCC_IO_BE_BF VCCO_BE, 1.2 V ‐ 3.3 V ‐ ‐ VCCO_BF VCC_IO_BO VCCO_BO 1.2 V ‐...
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Page 25: Signal Terminations
Details on the MIO/EMIO terminology are available in the Zynq UltraScale+ MPSoC Technical Reference Manual [21]. Some of the MIO pins on the Mercury+ XU6 SoC module are connected to on‐board peripherals, while others are available as GPIOs; the suggested functions below are for reference only ‐ always verify your MIO pinout with the Xilinx device handbook. -
Page 26: Analog Inputs
MIO Pins Function Connection [0:5] QSPI flash QSPI flash QSPI feedback clock Floating [7:8] LED2#, LED3# On‐board LEDs [9,23] Unused ‐ [10:11] On‐board I2C bus and module connector via level shifter [12] I2C interrupt On‐board I2C bus [13:22] eMMC flash eMMC flash [24:25] LED0#, LED1#... -
Page 27: Multi-Gigabit Transceiver ﴾Mgt
For optimal performance of high‐speed interfaces, for example, PCIe, use redrivers on the base board. The maximum data rate on the MGT lines on the Mercury+ XU6 SoC module depends on the routing path for these signals. When using MGTs at high performance rates, ensure adequate signal integrity over the full signal path. -
Page 28: Mgt Pairs
GTH Transceivers On modules equipped with ZU4 or ZU5 devices, there are 4 GTH MGTs available on the Mercury+ XU6 SoC module. Table describes the connections. The naming convention for the GTH MGT I/Os is: MGT_B<BANK>_<FUNCTION>_<PACKAGE_PIN>_<POLARITY>. For example, MGT_B224_TX2_R4_P is located on pin R4 of MGT I/O bank 224, it is a transmit pin and it has negative polarity. -
Page 29: Power
Power 2.10.1 Power Generation Overview The Mercury+ XU6 SoC module uses a 5 V to 15 V DC power input for generating the on‐board supply voltages. The power output pins of the module are accessible on the module connector. Table describes the power supplies generated on the module. -
Page 30: Power Enable/Power Good
1.8 V and 2.5 V. The list of regulators that can be disabled via PWR_EN signal is provided in Section 2.10.1. The PWR_EN input is pulled to VCC_3V3 on the Mercury+ XU6 SoC module with a 4.7 k resistor. The PWR_GOOD signal is pulled to VCC_3V3 on the Mercury+ XU6 SoC module with a 4.7 k resistor. -
Page 31: Voltage Supply Outputs
The voltage range applies to the default assembly option ﴾with LDO﴿. Table 16: Voltage Supply Inputs 2.10.4 Voltage Supply Outputs Table presents the supply voltages generated on the Mercury+ XU6 SoC module, that are available on the module connector. Supply Module Connector Pins Voltage Maximum... -
Page 32: Heat Dissipation
For Mercury modules an Enclustra heat sink kit is available for purchase along with the product. It rep‐ resents an optimal solution to cool the Mercury+ XU6 SoC module ‐ the heat sink body is low profile and usually covers the whole module surface. The kit comes with a gap pad for the MPSoC device, a fan and required mounting material to attach the heat sink to the module PCB and baseboard PCB. -
Page 33: Clock Generation
505. A 24 MHz clock and a 25 MHz clock are used for the USB PHYs and Ethernet PHYs respectively. The crystal pads for the MPSoC RTC are connected to a 32.768 kHz oscillator on the Mercury+ XU6 SoC module. -
Page 34: Reset
LEDs There are four active‐low user LEDs on the Mercury+ XU6 SoC module ‐ all of them are connected to both PS and PL. It is recommended to drive the PL pin to a high impedance state before driving the PS pin and vice versa. -
Page 35: Ddr4 Sdram ﴾Ps
2.14 DDR4 SDRAM ﴾PS﴿ There is a single DDR4 SDRAM channel on the Mercury+ XU6 SoC module attached directly to the PS side and is available only as a shared resource to the PL side. The DDR4 SDRAM is connected to PS I/O bank 504. The memory configuration on the Mercury+ XU6 SoC module supports ECC error detection and correction;... -
Page 36: Ddr4 Sdram Characteristics
16 bit Table 24: DDR4 SDRAM (PS) Characteristics 2.14.2 Signal Description Refer to the Mercury+ XU6 SoC Module FPGA Pinout Excel Sheet [4] for detailed information on the DDR4 SDRAM connections. 2.14.3 Termination No external termination is implemented for the data signals on the Mercury+ XU6 SoC module. Enclus‐... -
Page 37: Qspi Flash
QSPI Flash Characteristics Table describes the memory availability and configuration on the Mercury+ XU6 SoC module. As the Mercury+ XU6 SoC module is equipped with one QSPI flash chip, type “single” must be selected when programming the flash from Vivado tools. D‐0000‐464‐001 37 / Version 03, 24.10.2023... -
Page 38: Signal Description
Cypress ﴾Spansion﴿ Table 26: QSPI Flash Characteristics Different flash memory devices may be assembled in future revisions of the Mercury+ XU6 SoC module. Any flash memory with a different speed and temperature range fulfilling the requirements of the module variant may be used. -
Page 39: Signal Description
VCC_CFG_MIO must be set to 1.8 V. This boot mode has not been tested, but it may be supported in the future. 2.18 Gigabit Ethernet ﴾PS﴿ A 10/100/1000 Mbit Ethernet PHY is available on the Mercury+ XU6 SoC module, connected to the PS via RGMII interface. 2.18.1 Ethernet PHY Characteristics Table describes the Ethernet PHY ﴾PS﴿... -
Page 40: Mdio Address
RX and TX data, it is recommended to adjust the pad skew delays as specified in Table 29. These values have been successfully tested by Enclustra. The delays can be adjusted by programming the RGMII pad skew registers of the Ethernet PHY. Refer to the PHY datasheet for details. -
Page 41: Usb 2.0
USB 2.0 Two USB 2.0 PHYs are available on the Mercury+ XU6 SoC module, both connected to the PS to I/O bank 502. USB PHY 0 can be configured as host or device, while USB PHY 1 can be used only as host. -
Page 42: Display Port
﴾PMU﴿. More information on the PMU is available in the Zynq UltraScale+ MPSoC Technical Reference Manual [21]. The RTC crystal pad input and crystal pad output are connected on the Mercury+ XU6 SoC module to a 32.768 kHz oscillator. -
Page 43: Secure Eeprom
Type Manufacturer ATSHA204A‐MAHDA‐T ﴾default﴿ Atmel DS28CN01 ﴾assembly option﴿ Maxim Table 31: EEPROM Type An example demonstrating how to read data from the EEPROM is included in the Mercury+ XU6 SoC module reference design [2]. D‐0000‐464‐001 43 / Version 03, 24.10.2023... -
Page 44: Device Configuration
3 Device Configuration Configuration Signals The PS of the MPSoC needs to be configured before the FPGA logic can be used. Xilinx Zynq devices need special boot images to boot from QSPI flash, eMMC flash or SD card. For more information, refer to the Zynq UltraScale+ MPSoC Technical Reference Manual [21]. -
Page 45: Power-On Reset Delay Override
Figure 12: Pull‐Up During Configuration (PUDC) and Power‐on Reset Delay Override (PORSEL) Figure 13: Pull‐Up During Configuration (PUDC) and Power‐on Reset Delay Override (PORSEL) Resistors ‐ Assembly Drawing Bottom View (middle right part) For details on the PUDC signal, refer to the Zynq UltraScale+ MPSoC Technical Reference Manual [21]. Power‐on Reset Delay Override The power‐on reset delay override MPSoC signal ﴾POR_OVERRIDE﴿... -
Page 46: Boot Mode
Certain Xilinx tool versions support QSPI flash programming via JTAG only when JTAG boot mode is used ﴾unavailable on the Mercury+ XU6 SoC module﴿. Alternatively, the QSPI flash can be programmed in u‐boot or Linux by the SPI controller in the PS or from an SPI external master. -
Page 47: External Connectivity
The VREF pin of the programmer must be connected to VCC_CFG_MIO. It is recommended to add 22 series termination resistors between the module and the JTAG header, close to the source. Refer to the Enclustra Module Pin Connection Guidelines for details on JTAG interface. 3.5.3 JTAG Boot Mode JTAG boot mode is used explicitly for initial booting and is not required for the general JTAG mode used for programming, debugging, and in‐system testing. -
Page 48: Emmc Boot Mode
In the SD card boot mode the PS boots from the SD card located on the base board. There are two SD card boot modes available on the Mercury+ XU6 SoC module. The SD boot mode with level shifter is currently not supported. -
Page 49: Qspi Flash Programming From An External Spi Master
for details. For more information, refer to the Xilinx documentation [21] and support. Alternatively, the QSPI flash can be programmed in u‐boot or Linux by the SPI controller in the PS or from an SPI external master. 3.11 QSPI Flash Programming from an External SPI Master The signals of the QSPI flash are directly connected to the module connector for flash access, as shown in Table 36. -
Page 50: Enclustra Module Configuration Tool
3.12 Enclustra Module Configuration Tool When used in combination with an Enclustra base board, the QSPI flash can be programmed using En‐ clustra Module Configuration Tool ﴾MCT﴿ [19]. For this method, a non‐QSPI boot mode must be used during QSPI flash programming. The entire procedure is described in the reference design documenta‐... -
Page 51: I2C Communication
4 I2C Communication Overview The I2C bus on the Mercury+ XU6 SoC module is connected to the MPSoC device and to the EEPROM, and is available on the module connectors. This allows external devices to read the module type and to connect more devices to the I2C bus. -
Page 52: Secure Eeprom
Secure EEPROM The secure EEPROM is used to store the module serial number and configuration. An example demon‐ strating how to read the module information from the EEPROM memory is included in the Mercury+ XU6 SoC module reference design. Any attempt to write data to the secure EEPROM causes the warranty to be rendered void. -
Page 53: Module Configuration
Module Configuration Addr. Bits Comment Min. Value Max. Value Comment [7:4] MPSoC type See MPSoC type table ﴾Table 42﴿ 0x08 [3:0] MPSoC device speed grade [7:6] Temperature range See temperature range table ﴾Table 43﴿ Power grade 0 ﴾Normal﴿ 1 ﴾Low power﴿ [4:3] Gigabit Ethernet port count 0x09... -
Page 54: Mpsoc Device Types
Value MPSoC Device Type XCZU2CG XCZU2EG XCZU3EG XCZU4CG XCZU4EV XCZU5EV Table 42: MPSoC Device Types Table shows the available temperature ranges. Value Module Temperature Range Commercial Extended Industrial Table 43: Module Temperature Range Ethernet MAC Address The Ethernet MAC address is stored using big‐endian byte order ﴾MSB on the lowest address﴿. Each module is assigned two sequential MAC addresses;... -
Page 55: Absolute Maximum Ratings
5 Operating Conditions Absolute Maximum Ratings Table indicates the absolute maximum ratings for Mercury+ XU6 SoC module. The values given are for reference only. For details, refer to the Zynq UltraScale+ MPSoC, DC and AC Switching Characteristics Datasheet [23]. Parameter... -
Page 56: Recommended Operating Conditions
Recommended Operating Conditions Table indicates the recommended operating conditions for Mercury+ XU6 SoC module. The values given are for reference only. For details, refer to the Zynq UltraScale+ MPSoC, DC and AC Switching Characteristics Datasheet [23]. Parameter Description Rating Unit... - Page 57 6 Ordering and Support Ordering Use the Enclustra online request/order form for ordering or requesting information: http://www.enclustra.com/en/order/ Support Follow the instructions on the Enclustra online support site: http://www.enclustra.com/en/support/ D‐0000‐464‐001 57 / Version 03, 24.10.2023...
- Page 58 List of Figures Hardware Block Diagram ........10 Product Model Fields .
- Page 59 JTAG Interface ‐ PL and PS Access and Debug ......47 SD Card Boot Modes .
- Page 60 [1] Enclustra General Business Conditions http://www.enclustra.com/en/products/gbc/ [2] Mercury+ XU6 SoC Module Reference Design https://github.com/enclustra [3] Mercury+ XU6 SoC Module IO Net Length Excel Sheet Ask Enclustra for details [4] Mercury+ XU6 SoC Module FPGA Pinout Excel Sheet Ask Enclustra for details...
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