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Mercury+ XU7 SoC Module
Purpose
The purpose of this document is to present the characteristics of Mercury+ XU7 SoC module to the user,
and to provide the user with a comprehensive guide to understanding and using the Mercury+ XU7 SoC
module.
Summary
This document first gives an overview of the Mercury+ XU7 SoC module followed by a detailed description
of its features and configuration options. In addition, references to other useful documents are included.
Product Information
Product
Document Information
Reference / Version / Date
Approval Information
Written by
Verified by
Approved by
User Manual
Code
ME‐XU7
Reference
D‐0000‐443‐001
Name
DIUN, MMOS
MZEI
IJOS
Enclustra GmbH – Räffelstrasse 28 – CH‐8045 Zürich – Switzerland
Name
Mercury+ XU7 SoC Module
Version
10
Position
Design Engineer
Design Expert
Manager, BU‐SP
Phone +41 43 343 39 43 – www.enclustra.com
Date
30.01.2024
Date
03.09.2018
08.01.2024
30.01.2024
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Summary of Contents for Enclustra Mercury+ XU7
- Page 1 Mercury+ XU7 SoC Module User Manual Purpose The purpose of this document is to present the characteristics of Mercury+ XU7 SoC module to the user, and to provide the user with a comprehensive guide to understanding and using the Mercury+ XU7 SoC module.
- Page 2 Unauthorized duplication of this document, in whole or in part, by any means is prohibited without the prior written permission of Enclustra GmbH, Switzerland. Although Enclustra GmbH believes that the information included in this publication is correct as of the date of publication, Enclustra GmbH reserves the right to make changes at any time without notice.
- Page 3 Document History Version Date Author Comment 30.01.2024 MGOS Updated for revision 5.0 modules: added products, improved terminology, content, and layout for better readability and consistency 02.09.2022 TKAU Updated for revision 4.1 modules: added information on discontinuation of support for power converter switching frequency synchronisation, changes on base board descriptions 22.07.2021 MMOS...
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Page 4: Table Of Contents
1.3.2 Enclustra Build Environment ........ - Page 5 ..... . . 50 3.13 Enclustra Module Configuration Tool ....... . . 51 I2C Communication D‐0000‐443‐001...
- Page 6 Overview ..........52 Signal Description .
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Page 7: Overview
The Enclustra Build Environment [16] is available for the Mercury+ XU7 SoC module. This build system allows the user to quickly set up and run Linux on any Enclustra SoC module. It allows the user to choose the desired target and download all the required binaries, such as bitstream and FSBL ﴾First Stage Boot Loader﴿. -
Page 8: Safety Recommendations And Warnings
1.1.7 Electromagnetic Compatibility The Mercury+ XU7 SoC module is a Class A product ﴾as defined in IEC 61000‐3‐2 standard﴿ and is not intended for use in domestic environments. The product may cause electromagnetic interference, for which appropriate measures must be taken. -
Page 9: Deliverables
Enclustra Build Environment The Enclustra Build Environment ﴾EBE﴿ [16] enables the user to quickly set up and run Linux on any En‐ clustra SoC module or system board. It allows the user to choose the desired target, and download all the required binaries, such as bitstream and FSBL. -
Page 10: Petalinux Bsp
1.3.3 Petalinux BSP The Enclustra Petalinux BSPs enable the user to quickly set up a Petalinux project and to run Linux on the Enclustra SoC module or system board. The documentation [18] describes the build process in detail and allows a user without Petalinux knowl‐... -
Page 11: Amd Tool Support
AMD Tool Support The MPSoC devices assembled on the Mercury+ XU7 SoC module are supported by the Vivado ML Enterprise Edition software for which a paid license is required. Contact AMD for further information. D‐0000‐443‐001 11 / Version 10, 30.01.2024... -
Page 12: Module Description
Block Diagram Figure 1: Hardware Block Diagram The main component of the Mercury+ XU7 SoC module is the AMD Zynq UltraScale+ MPSoC device. Most of its I/O pins are connected to the Mercury+ module connector, making 136 regular user I/Os available to the user. -
Page 13: Module Configuration And Product Models
Table describes the available standard module configurations. The product model indicates the module type and main features. Figure describes the fields within the product model. Custom configurations are available. Contact Enclustra for more information. Product Model MPSoC DDR4 ECC DDR4 Temperature SDRAM ﴾PS﴿... -
Page 14: Module Label
EN-Number EN100000 SN123456 Serial Number Figure 3: Module Label The correspondence between EN‐number and product model for each revision is shown in Table 2. The known issues of the product and the changes between the revisions are described in the Mercury+ XU7 SoC Module Known Issues and Changes document [6]. -
Page 15: Top And Bottom Views
Top and Bottom Views Depending on the hardware revision and configuration, the module may look slightly different than shown in this document. 2.4.1 Top View Figure 4: Module Top View 2.4.2 Bottom View Figure 5: Module Bottom View D‐0000‐443‐001 15 / Version 10, 30.01.2024... -
Page 16: Top And Bottom Assembly Drawings
Top and Bottom Assembly Drawings Depending on the hardware revision and configuration, the module may look slightly different than shown in this document. 2.5.1 Top Assembly Drawing Figure 6: Module Top Assembly Drawing 2.5.2 Bottom Assembly Drawing Figure 7: Module Bottom Assembly Drawing D‐0000‐443‐001 16 / Version 10, 30.01.2024... -
Page 17: Module Footprint And Mechanical Data
Enclustra offers Mercury and Mercury+ modules of various geometries having widths of 56, 64, 65, 72 or 74 mm and having different topologies for the mounting holes. If different module types shall be fixed on the base board by screws, additional mounting holes may be required to accommodate different modules. -
Page 18: Module Connector
Ensure that the mounting holes on the base board are aligned with the mounting holes of the Mercury+ XU7 SoC module. Table describes the mechanical characteristics of the Mercury+ XU7 SoC module. A 3D model ﴾PDF﴿ and a STEP 3D model are available [8], [9]. Parameter... -
Page 19: User I/O
2.8.1 Pinout Information on the Mercury+ XU7 SoC module pins can be found in the Enclustra Mercury Master Pinout [11], and in the additional document Enclustra Module Pin Connection Guidelines [10]. The pin types on the schematic of the module connector and in the Master Pinout document are for reference only. -
Page 20: I/O Pin Exceptions
PCIe Reset Signal ﴾PERST#﴿ Table lists the I/O pin exceptions on the Mercury+ XU7 SoC module related to the PCIe reset connection. HD = high density pins, HP = high performance pins; Refer to the Zynq UltraScale+ MPSoC Overview [25] for details. -
Page 21: Differential I/Os
Table 6: I/O Pin Exceptions ‐ PERST# When the Mercury+ XU7 SoC module is used in combination with a Mercury+ PE1 base board as a PCIe device, the low value of the PERST# signal coming from the PCIe edge connector on the module con‐... -
Page 22: I/O Banks
The I/Os in the HD banks ﴾47, 48﴿ can be used only as differential inputs when LVDS/LVPECL standards are used; LVDS/LVPECL outputs are not supported. Internal differential termination is not supported for the HD pins; all differential signal pairs from both HD banks may optionally be equipped with 100 differential termination resistors on the module. -
Page 23: I/O Banks
C are used on other Enclustra modules; for compatibility purposes it is acceptable to power these pins even if they are not used on the Mercury+ XU7 SoC module. The Mercury+ XU7 SoC module may be used in combination with base boards having only two module connectors. -
Page 24: Signal Terminations
NOTICE Damage to the device due to unsuitable voltage Unsuitable voltages may damage the MPSoC device as well as other devices on the Mercury+ XU7 SoC module. Only use VCC_IO voltages compliant with the assembled MPSoC device. NOTICE Damage to the device due to floating VCC_IO pins Floating VCC_IO pins reduce ESD protection. -
Page 25: Multiplexed I/O ﴾Mio﴿ Pins
HD banks may optionally be equipped with 100 differential termination resistors on the module. The resistor identifiers for each differential input pair can be retrieved from the Mercury+ XU7 SoC Mod‐ ule User Schematics [5]. Single‐Ended Outputs There are no series termination resistors on the Mercury+ XU7 SoC module for single‐ended outputs. -
Page 26: Analog Inputs
MIO Pins Function Connection [40:41,43:44] User functionality Module connector PCIe block PERST# signal [42] Module connector User functionality SD card Module connector [45:51] User functionality [52:63] USB 0 USB 2.0 PHY 0 Ethernet 1 Gigabit Ethernet PHY 1 [64:75] USB 1 USB 2.0 PHY 1 [76:77] Ethernet MDIO... -
Page 27: Multi-Gigabit Transceiver ﴾Mgt
GTH Transceivers There are 16 GTH MGTs available on the Mercury+ XU7 SoC module organized in four FPGA banks ‐ Table describes the connections. The naming convention for the GTH MGT I/Os is: MGT_B<BANK>_<FUNCTION>_<PACKAGE_PIN>_<POLARITY>. -
Page 28: Mgt Pairs
MPSoC performance may be achieved. GTR Transceivers There are four GTR MGT pairs and two reference input clock differential pairs on the Mercury+ XU7 SoC module connected to I/O bank 505; these are routed to module connector B. -
Page 29: Power
Power 2.10.1 Power Generation Overview The Mercury+ XU7 SoC module uses a 5 V to 15 V DC power input for generating the on‐board supply voltages. Some of these voltages are accessible on the module connector. Table describes the power supplies generated on the module. -
Page 30: Power Enable/Power Good
1.8 V and 2.5 V. The list of regulators that can be disabled via PWR_EN signal is provided in Section 2.10.1. The PWR_EN input is pulled to VCC_3V3 on the Mercury+ XU7 SoC module with a 4.7 k resistor. The PWR_GOOD signal is pulled to VCC_3V3 on the Mercury+ XU7 SoC module with a 4.7 k... -
Page 31: Voltage Supply Inputs
2.10.3 Voltage Supply Inputs Table describes the power supply inputs on the Mercury+ XU7 SoC module. The VCC voltages used as supplies for the I/O banks are described in Section 2.8.5. Supply Name Module Connector Voltage Description Pins VCC_MOD A1, A2, A3, A4, A5, A6, 5 ‐... -
Page 32: Power Consumption
For Mercury modules an Enclustra heat sink kit is available for purchase along with the product. It rep‐ resents an optimal solution to cool the Mercury+ XU7 SoC module ‐ the heat sink body is low profile and usually covers the whole module surface. The kit comes with a gap pad for the MPSoC device, a fan and required mounting material to attach the heat sink to the module PCB and baseboard PCB. -
Page 33: Clock Generation
Clock Generation A 33.33 MHz oscillator is used for the Mercury+ XU7 SoC module clock generation; the 33.33 MHz clock is fed to the PS. A 100 MHz LVDS oscillator is connected to FPGA bank 65 and can serve as a reference for the PLL used to generate the clocks required for the PL DDR interface. -
Page 34: Reset
Pulling PS_POR# low resets the MPSoC device, the Ethernet and the USB PHYs, and the QSPI and eMMC flash devices. Refer to the Enclustra Module Pin Connection Guidelines [10] for general rules regarding the connection of reset pins. -
Page 35: Leds
2.13 LEDs There are three active‐low user LEDs on the Mercury+ XU7 SoC module ‐ two of them are connected to the PS and one connected to the PL. Signal Name Package Pin Pin Name Comment PS_LED0# MIO[24] User function / active‐low... -
Page 36: Signal Description
2.14.2 Signal Description Refer to the Mercury+ XU7 SoC Module FPGA Pinout Excel Sheet [4] for detailed information on the DDR4 SDRAM connections. 2.14.3 Termination No external termination is implemented for the data signals on the Mercury+ XU7 SoC module. Enclus‐... -
Page 37: Ddr4 Sdram ﴾Pl
16 bit Table 25: DDR4 SDRAM (PL) Characteristics 2.15.2 Signal Description Refer to the Mercury+ XU7 SoC Module FPGA Pinout Excel Sheet [4] for detailed information on the DDR4 SDRAM connections. 2.15.3 Termination No external termination is implemented for the data signals on the Mercury+ XU7 SoC module. Enclus‐... -
Page 38: Qspi Flash
Table describes the memory availability and configuration on the Mercury+ XU7 SoC module. As there is one QSPI flash chip assembled on the Mercury+ XU7 SoC module, type “single” must be selected when programming the flash from Vivado tools. Flash Type... -
Page 39: Configuration
The Mercury+ XU7 SoC module is equipped with a 16 GB eMMC flash. Different flash memory devices may be assembled in future revisions of the Mercury+ XU7 SoC module. Any flash memory with a different speed and temperature range fulfilling the requirements of the module variant may be used. -
Page 40: Ethernet Phy Characteristics
Ethernet PHYs are connected to the I2C interrupt signal line, which is available on the MIO pin 12. 2.19.3 External Connectivity The Ethernet signal lines can be connected directly to the magnetics. Refer to the Enclustra Module Pin Connection Guidelines [10] for details regarding the connection of Ethernet signals. D‐0000‐443‐001 40 /... -
Page 41: Mdio Address
RX and TX data, it is recommended to adjust the pad skew delays as specified in Table 31. These values have been successfully tested on Enclustra side. The delays can be adjusted by programming the RGMII pad skew registers of the Ethernet PHY. Refer to the PHY datasheet for details. -
Page 42: Usb 2.0
USB 2.0 Two USB 2.0 PHYs are available on the Mercury+ XU7 SoC module, both connected to the PS to I/O bank 502. USB PHY 0 can be configured as host or device and USB PHY 1 can be used only as host. -
Page 43: Display Port
USB 2.0 signals from the PHY, all routed to a USB 3.0 connector on the base board. The USB 3.0 interface on the Mercury+ XU7 SoC module uses the GTR signal lines ﴾MGTPS signals on module connector B﴿, and not the USB_SSRX_P/N and USB_SSTX_P/N signal lines on module connec‐... -
Page 44: Secure Eeprom
MPSoC Technical Reference Manual [21]. The RTC crystal pad input and crystal pad output are connected on the Mercury+ XU7 SoC module to a 32.768 kHz oscillator. A 1.5 V LDO is used to generate the battery voltage for the built‐in RTC ﴾supplied to VCC_PSBATT pin﴿, based on the VCC_BAT voltage mapped to the module connector. -
Page 45: Device Configuration
VCC_IO pins on connector C are not used, C_PRSNT# does not influence the behavior of the module. For compatibility with other Enclustra modules, it is recommended to connect C_PRSNT# to GND on the base board if the designed base board has three connectors. -
Page 46: Pull-Up During Configuration
Pull‐Up During Configuration The Pull‐Up During Configuration signal ﴾PUDC﴿ is pulled to GND on the module; as PUDC is an active‐ low signal, all FPGA I/Os will have the internal pull‐up resistors enabled during device configuration. If the application requires the pull‐up during configuration to be disabled, this can be achieved by re‐ moving R222 component and by mounting R221. -
Page 47: Boot Mode
The boot mode can be selected via two signals available on the module connector. Table describes the available boot modes on the Mercury+ XU7 SoC module. Starting with revision 2, JTAG boot mode has been introduced to increase the usability with AMD tools, which may report issues when programming the on‐board QSPI flash or when loading the FPGA bitstream... -
Page 48: Jtag On Module Connector
The VREF pin of the programmer must be connected to VCC_CFG_MIO. It is recommended to add 22 series termination resistors between the module and the JTAG header, close to the source. Refer to the Enclustra Module Pin Connection Guidelines [10] for details on JTAG interface. 3.6.3... -
Page 49: Emmc Boot Mode
In the SD card boot mode the PS boots from the SD card located on the base board. There are two SD card boot modes available on the Mercury+ XU7 SoC module, as described in Table 35. The SD boot mode with level shifter is currently not supported. -
Page 50: Emmc Flash Programming
3.10 eMMC Flash Programming The eMMC flash can be formatted and/or programmed in u‐boot or Linux, like a regular SD card. The boot image or independent partition files can be transmitted via Ethernet or copied from another storage device. Certain AMD tool versions support eMMC flash programming via JTAG. 3.11 QSPI Flash Programming via JTAG The AMD Vivado and SDK software offer QSPI flash programming support via JTAG. -
Page 51: Enclustra Module Configuration Tool
3.13 Enclustra Module Configuration Tool In combination with an Enclustra base board, the QSPI flash can be programmed using Enclustra Module Configuration Tool ﴾MCT﴿ [19]. For this method, a non‐QSPI boot mode must be used during QSPI flash programming. The entire procedure is described in the reference design documentation. -
Page 52: I2C Communication
4 I2C Communication Overview The I2C bus on the Mercury+ XU7 SoC module is connected to the MPSoC device and to the EEPROM, and is available on the module. This allows external devices to read the module type and to connect more devices to the I2C bus. -
Page 53: Secure Eeprom
Secure EEPROM The secure EEPROM is used to store the module serial number and configuration. An example demon‐ strating how to read the module information from the EEPROM memory is included in the Mercury+ XU7 SoC module reference design. Any attempt to write data to the secure EEPROM causes the warranty to be rendered void. -
Page 54: Module Configuration
Module Configuration Addr. Bits Description Min. Value Max. Value Comment [7:4] MPSoC type See MPSoC type ta‐ ble ﴾Table 43﴿ 0x08 [3:0] MPSoC device speed grade [7:6] Temperature range See temperature range table ﴾Table 44﴿ Power grade 0 ﴾Normal﴿ 1 ﴾Low power﴿ 0x09 [4:3] Gigabit Ethernet port count... -
Page 55: Module Temperature Range
Value Module Temperature Range Commercial Extended Industrial Table 44: Module Temperature Range Ethernet MAC Address The Ethernet MAC address is stored using big‐endian byte order ﴾MSB on the lowest address﴿. Each module is assigned two sequential MAC addresses; only the lower one is stored in the EEPROM. D‐0000‐443‐001 55 / Version 10, 30.01.2024... -
Page 56: Operating Conditions
5 Operating Conditions Absolute Maximum Ratings Table indicates the absolute maximum ratings for Mercury+ XU7 SoC module. The values given are for reference only. For details, refer to the Zynq UltraScale+ MPSoC, DC and AC Switching Characteristics Datasheet [23]. Parameter Description Min. -
Page 57: Recommended Operating Conditions
Recommended Operating Conditions Table indicates the recommended operating conditions for Mercury+ XU7 SoC module. The values given are for reference only. For details, refer to the Zynq UltraScale+ MPSoC, DC and AC Switching Characteristics Datasheet [23]. Parameter Description Min. Max. -
Page 58: Ordering And Support
6 Ordering and Support Ordering Use the Enclustra online request/order form for ordering or requesting information: http://www.enclustra.com/en/order/ Support Follow the instructions on the Enclustra online support site: http://www.enclustra.com/en/support/ D‐0000‐443‐001 58 / Version 10, 30.01.2024... -
Page 59: List Of Figures
List of Figures Hardware Block Diagram ........12 Product Model Fields . - Page 60 EEPROM Characteristics ......... 44 MPSoC Configuration Pins .
-
Page 61: References
[1] Enclustra General Business Conditions http://www.enclustra.com/gbc/ [2] Mercury+ XU7 SoC Module Reference Design https://github.com/enclustra [3] Mercury+ XU7 SoC Module IO Net Length Excel Sheet Ask Enclustra for details [4] Mercury+ XU7 SoC Module FPGA Pinout Excel Sheet https://www.enclustra.com/me-xu7-fpga-pinout [5] Mercury+ XU7 SoC Module User Schematics https://www.enclustra.com/me-xu7-user-schematic...
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