Reference Design Description; Microblaze System; Clocks; Microblaze Cpu - Enclustra Mars AX3 User Manual

2 Reference Design Description

Enclustra Mars PM3 Base Board
Enclustra Mars AX3 FPGA Module
Xilinx Artix-7 FPGA
QSPI
Flash
DDR3(L)
SDRAM
LEDs
Figure 1: Hardware Block Diagram
2.1

Microblaze System

2.1.1

Clocks

The Microblaze system runs on a 100 MHz clock generated by a PLL inside the Memory Interface Gener-
ator (MIG) IP core from an on-board 50 MHz LVDS oscillator.
2.1.2

Microblaze CPU

The Microblaze CPU has access to all peripheral devices via the AXI bus interconnect. The processor has a
fast internal memory of 64 kB, along with 8 kB instruction and 8 kB data cache for accesses to the external
DDR3/DDR3L SDRAM memory.
The size of the internal memory can be modified from the Address Editor tab in the block design, while
the cache dimensions can be modified from the Microblaze wizard.
2.1.3

DDR3/DDR3L SDRAM

The DDR3/DDR3L SDRAM memory runs at its corresponding maximum frequency at a voltage of 1.5 V by
default. These parameters can be modified in the Memory Interface Generator (MIG) IP core. In addition
to the IP core changes it is necessary to change the top level assignment of DDR3_VSEL signal from high
impedance to logic low for a voltage of 1.35V.
D-0000-492-002
Microblaze system
Local Memory
Microblaze CPU
SPI
Controller
Controller
SDRAM
Controller
GPIO GPIO UART
Ethernet
XADC
EEPROM
I2C
RTC
Ethernet
MAC PHY
5 / 24
User
EEPROM
System
Monitor
FTDI USB Micro USB
Device Connector
Connector
Version 2022.1_v1.0.2, 04.01.2023
RJ45