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Mercury+ XU9 SoC Module
Purpose
The purpose of this document is to present the characteristics of Mercury+ XU9 SoC module to the user,
and to provide the user with a comprehensive guide to understanding and using the Mercury+ XU9 SoC
module.
Summary
This document first gives an overview of the Mercury+ XU9 SoC module followed by a detailed description
of its features and configuration options. In addition, references to other useful documents are included.
Product Information
Product
Document Information
Reference / Version / Date
Approval Information
Written by
Verified by
Approved by
User Manual
Code
ME-XU9
Reference
D-0000-463-001
Name
DIUN, MMOS
MMOS, GKOE
SJOK
Enclustra GmbH – Räffelstrasse 28 – CH-8045 Zürich – Switzerland
Name
Mercury+ XU9 SoC Module
Version
04
Position
Design Engineer
Design Expert
Product Manager
Phone +41 43 343 39 43 – www.enclustra.com
Date
05.09.2022
Date
20.05.2019
24.05.2019
05.09.2022
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Related Manuals for Enclustra Mercury Plus XU9
Summary of Contents for Enclustra Mercury Plus XU9
- Page 1 Position Date Written by DIUN, MMOS Design Engineer 20.05.2019 Verified by MMOS, GKOE Design Expert 24.05.2019 Approved by SJOK Product Manager 05.09.2022 Enclustra GmbH – Räffelstrasse 28 – CH-8045 Zürich – Switzerland Phone +41 43 343 39 43 – www.enclustra.com...
- Page 2 Unauthorized duplication of this document, in whole or in part, by any means is prohibited without the prior written permission of Enclustra GmbH, Switzerland. Although Enclustra GmbH believes that the information included in this publication is correct as of the date of publication, Enclustra GmbH reserves the right to make changes at any time without notice.
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Page 3: Table Of Contents
Enclustra Build Environment ........ - Page 4 3.13 Enclustra Module Configuration Tool ....... . . 51 I2C Communication Overview .
- Page 5 Signal Description ..........52 I2C Address Map .
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Page 6: Overview
The Enclustra Build Environment [16] is available for the Mercury+ XU9 SoC module. This build system allows the user to quickly set up and run Linux on any Enclustra SoC module. It allows the user to choose the desired target and download all the required binaries, such as bitstream and FSBL (First Stage Boot Loader). -
Page 7: Electrostatic Discharge
Ensure that the power supply is disconnected from the board before inserting or removing the Mercury+ XU9 SoC module, connecting interfaces, or connecting jumpers. Touching the capacitors of the DC-DC converters can lead to voltage peaks and permanent damage; over-voltage on power or signal lines can also cause permanent damage to the module. 1.1.6 Electrostatic Discharge Electronic boards are sensitive to electrostatic discharge (ESD). -
Page 8: Deliverables
1.4.3 Petalinux BSP The Enclustra Petalinux BSPs enable the user to quickly set up a Petalinux project and to run Linux on the Enclustra SoC module or system board. The documentation [18] describes the build process in detail and allows a user without Petalinux knowl- edge to build and run the desired design on the target hardware. -
Page 9: Enclustra Heat Sink
FMC interfaces, the compatibility of the Mercury+ XU9 SoC module to the Mercury+ PE1 base board is limited. It is recommended to check the FMC card pinout in detail with the Enclustra Mercury Master Pinout and with the module and base board schematics. -
Page 10: Xilinx Tool Support
Xilinx Tool Support The MPSoC devices equipped on the Mercury+ XU9 SoC module are supported by the Vivado HL Web- PACK Edition software, which is available free of charge. Please contact Xilinx for further information. D-0000-463-001 10 / 61 Version 04, 05.09.2022... -
Page 11: Module Description
2 Module Description Block Diagram Figure 1: Hardware Block Diagram The main component of the Mercury+ XU9 SoC module is the Xilinx Zynq UltraScale+ MPSoC device. All available I/O pins (which are not routed to on-board peripherals) are connected to the Mercury+ module connector, making 92 regular user I/Os available to the user. -
Page 12: Module Configuration And Product Models
Figure 2: Product Model Fields Please note that for the first revision modules or early access modules, the product model may not respect entirely this naming convention. Please contact Enclustra for details on this aspect. EN-Numbers and Part Names Every module is uniquely labeled, showing the EN-number and serial number. An example is presented in Figure 3. -
Page 13: Module Label
Figure 3: Module Label The correspondence between EN-number and part name is shown in Table 2. The part name represents the product model, followed by the revision; the R suffix and number represent the revision number. The revision changes and product known issues are described in the Mercury+ XU9 SoC Module Known Issues and Changes document [6]. -
Page 14: Top And Bottom Views
Top and Bottom Views 2.4.1 Top View Figure 4: Module Top View 2.4.2 Bottom View Figure 5: Module Bottom View Please note that depending on the hardware revision and configuration, the module may look slightly different than shown in this document. D-0000-463-001 14 / 61 Version 04, 05.09.2022... -
Page 15: Top And Bottom Assembly Drawings
Top and Bottom Assembly Drawings 2.5.1 Top Assembly Drawing Figure 6: Module Top Assembly Drawing 2.5.2 Bottom Assembly Drawing Figure 7: Module Bottom Assembly Drawing Please note that depending on the hardware revision and configuration, the module may look slightly different than shown in this document. -
Page 16: Module Footprint
Figure 8 shows the dimensions of the module footprint on the base board. Enclustra offers Mercury and Mercury+ modules of various geometries having widths of 56, 64, 65, 72 or 74 mm and having different topologies for the mounting holes. If different module types shall be fixed on the base board by screws, additional mounting holes may be required to accommodate different modules. -
Page 17: Mechanical Data
Mechanical Data Table 3 describes the mechanical characteristics of the Mercury+ XU9 SoC module. A 3D model (PDF) and a STEP 3D model are available [8], [9]. Symbol Value Size 54 mm Component height top 3.00 mm Component height bottom 1.35 mm Weight 32 g... -
Page 18: User I/O
User I/O 2.9.1 Pinout Information on the Mercury+ XU9 SoC module pinout can be found in the Enclustra Mercury Master Pinout [11], and in the additional document Enclustra Module Pin Connection Guidelines [10]. Warning! Please note that the pin types on the schematics symbol of the module connector and in the Master Pinout document are for reference only. -
Page 19: I/O Pin Exceptions
The naming convention for the user I/Os located in HD banks is: IO_B<BANK_LETTER>_L<PAIR><_SPECIAL_FUNCTION>_<PACKAGE_PIN>_<POLARITY> For example, IO_BN_L7_HDGC_AD5_E13_N is located on pin E13 of I/O bank N, pair 7, it is a System Monitor differential auxiliary analog input capable pin and also a clock capable pin and it has negative polarity, when used in a differential pair. -
Page 20: I/O Pin Exceptions - Perst
Using a PCIe block in the PL simultaneously with Gigabit Ethernet 0 interface on the PS side is possible. Simultaneous usage of two PCIe endpoints on the PL and PS sides is not supported and was not tested on Enclustra side. In situations in which PCIe functionality is not required, PS_MIO42_PERST# pin can be used in the same manner as a regular MIO pin. -
Page 21: Differential I/Os
2.9.3 Differential I/Os When using differential pairs, a differential impedance of 100 must be matched on the base board, and the two nets of a differential pair must have the same length. The information regarding the length of the signal lines from the MPSoC device to the module connector is available in Mercury+ XU9 SoC Module IO Net Length Excel Sheet [3]. -
Page 22: Vcc_Io Usage
FPGA banks which are powered by fixed voltages generated on the module. Note that the VCC_IO pins on connectors B and C are used on other Enclustra modules; for compatibility purposes it is acceptable to power these pins even if they are not used on the Mercury+ XU9 SoC module. -
Page 23: Signal Terminations
Warning! Use only VCC_IO voltages compliant with the equipped MPSoC device; any other voltages may dam- age the equipped MPSoC device, as well as other devices on the Mercury+ XU9 SoC module. Do not leave a VCC_IO pin floating, as this may damage the equipped MPSoC device, as well as other devices on the Mercury+ XU9 SoC module. -
Page 24: Multiplexed I/O (Mio) Pins
2.9.7 Multiplexed I/O (MIO) Pins Details on the MIO/EMIO terminology are available in the Zynq UltraScale+ MPSoC Technical Reference Manual [21]. Some of the MIO pins on the Mercury+ XU9 SoC module are connected to on-board peripherals, while others are available as GPIOs; the suggested functions below are for reference only - always verify your MIO pinout with the Xilinx device handbook. -
Page 25: Analog Inputs
2.9.8 Analog Inputs The Zynq UltraScale+ MPSoC devices contain a system monitor in the PL and an additional system mon- itor block in the PS. These are used to sample analog inputs and to collect information on the internal voltages and temperatures. The system monitor block in the PL provides a 10-bit ADC, which supports up to 17 external analog lines (1 dedicated differential input, 16 auxiliary differential inputs). -
Page 26: Mgt Pairs
GTH bank 224 for ZU7 devices MGT bank B represents: GTH bank 224 for ZU4/ZU5 devices GTH bank 225 for ZU7 devices MGT bank C represents: GTH bank 225 for ZU4/ZU5 devices GTH bank 226 for ZU7 devices MGT bank D represents: GTH bank 226 for ZU4/ZU5 devices GTH bank 227 for ZU7 devices The naming convention for the GTH MGT I/Os is:... -
Page 27: Power
Warning! It is recommended to use redrivers on the base board for PCIe Gen3 or other high-speed interfaces implementations, and to perform channel simulation. GTR Transceivers There are four GTR MGT pairs and two reference input clock differential pairs on the Mercury+ XU9 SoC module connected to I/O bank 505;... -
Page 28: Power Generation Overview
-3E MPSoC device is equipped, an assembly option is available to switch the PS core operating voltage to 0.9 V. Please refer to the Enclustra Module Pin Connection Guidelines for general rules on the power pins [10]. Power Converter Synchronization Starting with revision 2.1 modules, the switching converters used on the Mercury+ XU9 SoC module are... -
Page 29: Power Enable/Power Good
2.11.2 Power Enable/Power Good The Mercury+ XU9 SoC module provides a power enable input on the module connector. This input may be used to shut down the DC/DC converters and LDOs for 0.72/0.85/0.9 V, 0.85/0.9 V, 0.9 V, 1.2 V, 1.8 V and 2.5 V. -
Page 30: Voltage Supply Outputs
MPSoC is adequately cooled. For Mercury modules an Enclustra heat sink kit is available for purchase along with the product. It rep- resents an optimal solution to cool the Mercury+ XU9 SoC module - the heat sink body is low profile and usually covers the whole module surface. -
Page 31: Voltage Monitoring
B-167 VCC_0V9 0.9 V on-board voltage VMON_1V2 VCC_1V2 1.2 V on-board voltage Table 18: Voltage Monitoring Outputs Warning! The voltage monitoring outputs are for Enclustra-use only. Pinout changes may be applied between revisions. D-0000-463-001 31 / 61 Version 04, 05.09.2022... -
Page 32: Clock Generation
Pulling PS_POR# low resets the MPSoC device, the Ethernet and the USB PHYs, and the QSPI and eMMC flash devices. Please refer to the Enclustra Module Pin Connection Guidelines [10] for general rules re- garding the connection of reset pins. -
Page 33: Leds
Signal Name Connector Pin Package Pin FPGA Pin Type Description PS_POR# A-132 PS_POR_B Power-on reset PS_SRST# A-124 PS_SRST_B System reset Table 20: Reset Resources Please note that PS_POR# is automatically asserted if PWR_GOOD is low. 2.14 LEDs There are three active-low user LEDs on the Mercury+ XU9 SoC module - two of them are connected to the PS and one connected to the PL. -
Page 34: Ddr4 Sdram Type
2.15.1 DDR4 SDRAM Type Table 23 describes the memory availability and configuration on the Mercury+ XU9 SoC module. Module SDRAM Type Density Configuration Manufact. ME-XU9-D11E (industrial) K4A4G165WE-BIRC 4 Gbit 256 M 16 bit Samsung ME-XU9-D12E (industrial) K4A8G165WB-BIRC 8 Gbit 512 M 16 bit Samsung Table 23: DDR4 SDRAM (PS) Types... -
Page 35: Ddr4 Sdram (Pl)
Parameter Value Memory type DDR4 DRAM bus width 64 bit Enabled DRAM chip bus width 16 bits DRAM chip capacity 4096-8192 Mbits Bank group address count Bank address count Row address count 15-16 Column address count Speed bin DDR4 2400T Operating frequency 1200 MHz CAS latency... -
Page 36: Ddr4 Sdram Type
2.16.1 DDR4 SDRAM Type Table 23 describes the memory availability and configuration on the Mercury+ XU9 SoC module. Module SDRAM Type Density Configuration Manufact. Any module variant (extended) MT40A256M16GE-083E 4 Gbit 256 M 16 bit Micron Any module variant (extended) H5AN4G6NAFR-UHC 4 Gbit 256 M... -
Page 37: Qspi Flash
Parameter Value Memory Device Interface Speed (ps) Reference Input Clock Speed (ps) 10000 (100 MHz) Memory Part MT40A256M16 Data Width Data Mask and DBI DM NO DBI Cas Latency Cas Write Latency Table 26: DDR4 SDRAM (PL) Parameters 2.17 QSPI Flash The QSPI flash can be used to boot the PS, and to store the FPGA bitstream, ARM application code and other user data. -
Page 38: Configuration
Warning! Special care must be taken when connecting the QSPI flash signals on the base board. Long traces or high capacitance may disturb the data communication between the MPSoC and the flash device. 2.17.3 Configuration The QSPI flash supports up to 50 MHz operation for standard read. For fast, dual and quad read speed values, please refer to the flash device datasheet. -
Page 39: Signal Description
2.18.2 Signal Description The eMMC flash signals are connected to the MIO pins 13-22 for 8-bit data transfer mode. The command signal has a 4.7 k pull-up resistor to 1.8 V and the data lines have 47 k pull-up resistors to 1.8 V. 2.19 SD Card An SD card can be connected to the PS MIO pins 45-51. -
Page 40: External Connectivity
Ethernet PHYs is connected to the I2C interrupt line, available on MIO pin 12. 2.20.3 External Connectivity The Ethernet signal lines can be connected directly to the magnetics. Please refer to the Enclustra Module Pin Connection Guidelines [10] for details regarding the connection of Ethernet signals. 2.20.4... -
Page 41: Rgmii Delays Configuration
Signal Value Description MODE[3-0] 1110 RGMII mode: advertise all capabilities (10/100/1000, half/full duplex) except 1000Base-T half duplex. PHY0: MDIO address 3 PHYAD[2-0] PHY1: MDIO address 7 Clk125_EN 125 MHz clock output disabled LED_MODE Single LED mode LED1/LED2 Active-low LEDs Table 31: Gigabit Ethernet PHYs Configuration - Bootstraps For the Ethernet PHY configuration via the MDIO interface, the MDC clock frequency must not exceed 2 MHz. -
Page 42: Signal Description
PHY Type Manufacturer Type USB3320C Microchip USB 2.0 PHY Table 33: USB 2.0 PHY Type 2.21.2 Signal Description The ULPI interface for the PHY 0 is connected to MIO pins 52-63 for use with the integrated USB controller. The ULPI interface for the PHY 1 is connected to MIO pins 64-75. The MIO signals are shared between Ethernet PHY 1 and USB PHY 1, therefore only one of them can be used. -
Page 43: Display Port
A 1.2 V LDO is used to generate the battery voltage for the built-in RTC (supplied to VCC_PSBATT pin), based on the VCC_BAT voltage mapped to the module connector. This pin can be connected directly to a 3 V battery on the base board. Please refer to the Enclustra Module Pin Connection Guidelines [10] for details. -
Page 44: Secure Eeprom
2.25 Secure EEPROM The secure EEPROM is used to store the module type and serial number, as well as the Ethernet MAC address and other information. It is connected to the I2C bus. The secure EEPROM must not be used to store user data. Please refer to Section 4.4 for details on the content of the EEPROM. -
Page 45: Device Configuration
3 Device Configuration Configuration Signals The PS of the MPSoC needs to be configured before the FPGA logic can be used. Xilinx Zynq devices need special boot images to boot from QSPI flash, eMMC flash or SD card. For more information, please refer to the Zynq UltraScale+ MPSoC Technical Reference Manual [21]. -
Page 46: Module Connector C Detection
VCC_IO pins on connector C are not used, C_PRSNT# does not influence the behavior of the module. For compatibility with other Enclustra modules, it is recommended to connect C_PRSNT# to GND on the base board if the designed base board has three connectors. -
Page 47: Power-On Reset Delay Override
Figure 13: Pull-Up During Configuration (PUDC) and Power-on Reset Delay Override (PORSEL) Resistors - Assembly Drawing Bottom View (lower right part) For details on the PUDC signal please refer to the Zynq UltraScale+ MPSoC Technical Reference Manual [21]. Power-on Reset Delay Override The power-on reset delay override MPSoC signal (POR_OVERRIDE) is pulled to GND on the module, set- ting the PL power-on delay time to the default standard time. -
Page 48: Jtag
BOOT BOOT Mode Description Remarks MODE1 MODE0 Straps [3:0] 0110 Boot from eMMC flash 1110 Boot from SD card (with an ex- Not supported (may be sup- ternal SD 3.0 compliant level ported in the future) shifter; only available when VCC_CFG_MIO is 1.8 V) 0010 Boot from QSPI flash... -
Page 49: External Connectivity
The VREF pin of the programmer must be connected to VCC_CFG_MIO. It is recommended to add 22 series termination resistors between the module and the JTAG header, close to the source. Please refer to the Enclustra Module Pin Connection Guidelines for details on JTAG interface. 3.6.3... -
Page 50: Emmc Boot Mode
3.3 V and afterwards it will command the card to drop from 3.3 V operation to 1.8 V operation. For this mode, an external SD 3.0 compliant level shifter is required. This boot mode may be supported in the future by Enclustra modules and base boards. BOOT_MODE1... -
Page 51: Qspi Flash Programming From An External Spi Master
3.13 Enclustra Module Configuration Tool In combination with an Enclustra base board, the QSPI flash can be programmed using Enclustra Module Configuration Tool (MCT) [19]. For this method, a non-QSPI boot mode must be used during QSPI flash programming. The entire procedure is described in the reference design documentation. -
Page 52: I2C Communication
4 I2C Communication Overview The I2C bus on the Mercury+ XU9 SoC module is connected to the MPSoC device and to the EEPROM, and is available on the module and debug connectors. This allows external devices to read the module type and to connect more devices to the I2C bus. -
Page 53: Secure Eeprom
An example demonstrating how to read the module information from the EEPROM memory is included in the Mercury+ XU9 SoC module reference design. Warning! The secure EEPROM is for Enclustra use only. Any attempt to write data to the secure EEPROM causes the warranty to be rendered void. 4.4.1... -
Page 54: Product Information
Module Product Family Reserved Revision Product Information Mercury+ XU9 SoC module 0x0336 0x[XX] 0x[YY] 0x0336 [XX][YY] Table 42: Product Information Module Configuration Addr. Bits Comment Min. Value Max. Value Comment MPSoC type See MPSoC type table (Table 44) 0x08 MPSoC device speed grade Temperature range See temperature range table (Table 45) -
Page 55: Module Temperature Range
Value Module Temperature Range Commercial Extended Industrial Table 45: Module Temperature Range Ethernet MAC Address The Ethernet MAC address is stored using big-endian byte order (MSB on the lowest address). Each module is assigned two sequential MAC addresses; only the lower one is stored in the EEPROM. D-0000-463-001 55 / 61 Version 04, 05.09.2022... -
Page 56: Operating Conditions
5 Operating Conditions Absolute Maximum Ratings Table 46 indicates the absolute maximum ratings for Mercury+ XU9 SoC module. The values given are for reference only; for details please refer to the Zynq UltraScale+ MPSoC, DC and AC Switching Charac- teristics Datasheet [23]. Symbol Description Rating... -
Page 57: Recommended Operating Conditions
Recommended Operating Conditions Table 47 indicates the recommended operating conditions for Mercury+ XU9 SoC module. The values given are for reference only; for details please refer to the Zynq UltraScale+ MPSoC, DC and AC Switching Characteristics Datasheet [23]. Symbol Description Rating Unit VCC_MOD... -
Page 58: Ordering And Support
6 Ordering and Support Ordering Please use the Enclustra online request/order form for ordering or requesting information: http://www.enclustra.com/en/order/ Support Please follow the instructions on the Enclustra online support site: http://www.enclustra.com/en/support/ D-0000-463-001 58 / 61 Version 04, 05.09.2022... - Page 59 List of Figures Hardware Block Diagram ........11 Product Model Fields .
- Page 60 Boot Modes ..........48 JTAG Interface - PL and PS Access and Debug .
- Page 61 [14] Mercury+ ST1 User Manual Ask Enclustra for details [15] Mercury+ PE3 User Manual Ask Enclustra for details [16] Enclustra Build Environment https://github.com/enclustra-bsp [17] Enclustra Build Environment How-To Guide https://github.com/enclustra/EBEAppNote [18] Petalinux BSP and Documentation https://github.com/enclustra/PetalinuxDocumentation [19] Enclustra Module Configuration Tool http://www.enclustra.com/en/products/tools/module-configuration-tool/...
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