Vitis Workspace Preparation; Fpga Bitstream Generation Step-By-Step Guide - Enclustra Mars AX3 User Manual

Step Description
4 Export the hardware system information (required for the Vitis IDE):
1. File
2. Select Include Bitstream and click Next
3. Leave the file name and export location as default and click Next
4. Click Finish
Table 5: FPGA Bitstream Generation Step-By-Step Guide
Please note that without Tri-Mode Ethernet MAC and Tri-Mode Ethernet MAC Controller licenses (Per-
manent or Evaluation), the FPGA bitstream generation will not be permitted.
Please contact Xilinx support for details.
3.4

Vitis Workspace Preparation

This section describes how to create and run software example applications. The steps are generic, and
apply to the software example templates in the Vitis IDE.
A pre-generated binary file of the HelloWorld example application and a hardware description file for
any AX3 variant is released on the AX3 Reference Design Github page.
Step Description
1 Start the Vitis IDE 2022.1
1. Select any workspace (e.g. <base_dir>\workspace)
2 Create a new Platform Project
1. File
2. In the New Platform Project:
(a) For Project Name type the <project_name> e.g. Mars_AX3_PM3
(b) Hit Next
(c) Select "Create a new platform from hardware (XSA)"
(d) Hit the Browse button and select the Hardware Specification .xsa file you exported
from Vivado, as described in Section 3.3.
The default export location used by Vivado is
<base_dir>\<vivado_proj_dir>\<project_name>.xsa Alternatively, the pre-
compiled hardware description file may be used.
(e) Wait for the file to be analyzed
(f) For the Operating System select standalone
(g) For the Processor select CPU_Microblaze_CPU
(h) Hit Finish and wait for completion
(i) Build the platform by pressing Ctrl-B and wait for completion
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D-0000-492-002
Export Export Hardware and click Next
New Platform Project
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