Renesas R0E424270MCU00 User Manual page 125

R0E424270MCU00 User's Manual
The following items are shown in the Trace window (in bus display mode).
Table 5.13 Items shown in the Trace window
Column
Cycle Number of the cycle within trace memory. By default, the number of the last cycle to have been acquired
is 0, and earlier cycles are assigned progressively lower numbers in sequence, i.e. –1, –2, etc. If a delay
count is set, the cycle on which the trace stop condition is met is numbered 0 and the cycles that were
executed until the program actually stopped (cycles during a delay period) are assigned progressively
larger numbers +1, +2, etc. in sequence up to the last cycle to be acquired.
Label Label corresponding to the address (displayed only when a label has been set)
Address Address on the address bus
Data Data on the data bus (in hexadecimal)
Size Unit of access (byte, word, or longword)
Data bus state, indicated as "R" for reading, "W" for writing, or "–" for no access
R/W
Whether the bus cycle is valid or not. The value "0" indicates a valid bus cycle. The Address, Data and
RWT
BIU information is valid when RWT is "0".
Status Operating state of the target MCU.
Display form
DMAC
DTC
HUDI
DATA
FETCH
SLEEP DMAC
SLEEP DTC
SLEEP HUDI
SLEEP
AMCS
NONE
Area Area being accessed.
Display form
EXT16
EXT8
EXTMEM16
EXTMEM8
ROM
DATAFLASH
I/O16
I/O8
RAM
DTCRAM32
NONE
IMD0 States of interrupt mask bits of the condition code register in interrupt control mode 0.
Display form
.
I
-
R20UT3586EJ0202 Rev.2.02
Sep.01.21
Description
Description
Access by DMAC operation
Access by DTC operation
Access by HUDI operation
Data access by CPU operation
Instruction fetch by CPU operation
Sleeping due to DMAC operation
Sleeping due to DTC operation
Sleeping due to HUDI operation
CPU is in the sleep mode
Supply of clock signal to all modules is stopped.
No access
Description
16-bit external space
8-bit external space
16-bit external emulation memory
8-bit external emulation memory
Internal ROM
Data flash
Internal I/O space (16-bit I/O)
Internal I/O space (8-bit I/O)
Internal RAM
Internal RAM (32 bits) accessed due to DTC operation
No access
Description
Bit CCR I
0
1
The entry under IMD0 is "-" if IMD2 values are being displayed.
5. Debugging Functions
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