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2- PHASE
CLOCK
~I
ADBIO
ADX
OCP
MODE
CONTROL
OTBI I
COMPUTER
CONTROL
SMK
LOGIC
Pl LOO-
START/STOP
INPUT/OUTPUT
MODE
AD BOS
THRU
ADB
16
COMPUTER
CONTROL
PULSES
ADDRESS
DECODER
ADX
OTB09
OTB
THRU ........
GATING
OTB 16
'3648
ADX
DATA
SEQUENCE
CONTROL~------
......
-~
SHIFT
LOGIC
SHIFT
PULSES
BUFFER
BUFFER
STATUS
DATA
SKS
LOGIC
ORLIN-
t-------.., 1
REGISTER
1---------~•1
I NB
GATING
INB09
THRU
I NBl6
(9 bits)
D _A_T_A _____
sco1
Lwl~
11---------t . .
•ASR STOP
S H I F T
A SR
DAT A T 0
PULSES_.ENCODER/.._-------------....-AND FROM
DECODER
ASR
Figure 2-30.
ASR Interface Block Diagram
2-47
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