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NAND TYPE 2 PAC, MODEL DL-335
The NAND Type
2
PAC, Model DL-335 (Figures A-78 and A-79), contains six
4-input NAND gates.
Each gate performs the NAND function for positive logic, (+6v
=
ONE,
Ov
=
ZERO).
For negative logic, it becomes a NOR gate.
Two of the six gates have separate load connections available at the PAC terminals.
Outputs of these gates can be tied together, using a single load resistor, without loss of
output drive capability.
INPUT AND OUTPUT SIGNALS
Inputs. - - When all inputs to a gate are at +6v or not connected, the
~>utput
is at
ground.
When any input is at ground, the output is at +6v.
Load. -- This point is internally connected through a collector load resistor to +6v.
Collector Output. - - The collector output of any gate must be connected to at least
one collector resistor, either internal or external to the module.
Output. -- Each output terminal is internally connected to a collector load resistor.
If an output is connected to load points or other outputs, the output drive capability of the
structure is reduced.
SPECIFICATIONS
Frequency of Operation (System)
DC to 5 me
Input Loading
l
unit load each
Fan-In
Refer to general specifications.
Output Drive Capability
8 unit loads each
Outputs in Parallel
Refer to general specifications.
APPLICATIONS
Circuit Delay
(Measured at+ l. 5v, averaged over two
stages)
30 nsec (max)
Current Requirements
t6v:
75 ma (max)
Power Dissipation
0. 45w (max)
Handle Color Code
Red
The NAND gates operate on levels or pulses, or combinations of both.
Two gates
can be wired back to back to form a de set- reset flip-flop.
The two gates with separate load outputs form standard NAND gates when the load
and collector output terminals are connected.
When the collector outputs of such gates are
connected in parallel as in Figure A-80, the AND-OR-INVERT function is performed.
At
the point where the outputs are tied together, an AND operation with logic ONEs (OR opera-
tion with logic ZEROs) takes place.
A-137
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