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Input Loading
DC inputs:
Clock input:
Control inputs:
Output Drive Capability
2
I
3 unit load
unit load
1 unit load
8 unit loads (both outputs)
(Capable of also driving 75 pf total capacitance with delays as specified.)
Circuit Delay
The following circuit delays are specified from the +l. 5v level of thP, input Rignal
to the +l. 5v level of the output signal.
Clock input (ONE to ZERO transition)
{ 45
nsec (typ)
to latest output
60 nsec (max)
DC set input to set output or
f
65 nsec (typ)
DC reset input to reset output
l
80 nsec (max)
DC set input to reset output or
~
45 nsec (typ)
DC reset input to set output
l
60 nsec (max)
Clock and Control Input Timing Requirements
To trigger the flip-flop at the clock or control inputs, pulses must meet the require-
ments shown in Figure A-14.
DC Input Timing Requirements
To activate a de input, signals must meet the requirements of Figure A-15.
Control Inputs
Figure A-16 shows the timing requirements of the set and reset control inputs when
they are being used to steer the triggering clock input to set the flip-flop.
The reset con-
trol input must be completely switched to logic ZERO before the clock starts positive.
No
control input should go from logic ONE to ZERO while the clock is positive.
The set contro.l
input must be switched to logic ONE at least 40 nsec before the clock starts towards logic
ZERO.
The clock must be a positive pulse of 40 nsec minimum duration.
The flip-flop
changes state on the trailing edge of the positive clock pulse.
Reset timing is the same,
except that the time relations and logic levels of the set and reset input must be interchanged.
A-21
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