Table of Contents
Advertisement
COUNTER PAC, MODEL CC-088
The Counter PAC, Model CC-088 (Figures A-41 and A-42), contains six independent
flip-flops that can be used for counting, frequency division, and buffer storage.
Each stage
has a complement input, de set and de reset inputs, and set and reset outputs.
There is also
a common reset input for clearing all stages simultaneously.
Application of a signal to the
complement input causes the flip-flop to change state.
(Toggling action is accomplished
without additional wiring.)
INPUT AND OUTPUT SIGNALS
DC Set and Reset. --
A signal at Ov for 80 nsec or longer on the de set (or reset)
input will set (or reset) the flip-flop.
Common Reset. -- A signal at Ov for 80 nsec or longer on the common reset input
will clear the six counter stages simultaneously.
Complement. --
The output changes state on the negative transition of the com-
plement input.
This input is the same as the clock input of the integrated circuit flip-flop.
SPECIFICATIONS
Frequency of Operation (System)
DC to 5 me
Input Loading
DC inputs:
Common reset:
Complement:
2/3 unit load each
4 unit loads
1 unit load each
Output Drive Capability
8 unit loads each
Handle Color Code
Blue
APPLICATIONS
Circuit Delay
Complement input to flip-flop
outputs (counter propagation
stage delay):
60 nsec (max)
DC set input to set output, or
de res et input to res et
output:
80 ns ec (max)
DC set input to reset output, or
reset input to set ouput:
60 nsec(max)
Current Requirements
+6v:
150 ma (max)
Power Dissipation
O. 90w
(max)
Each of the stages can be used separately for divide-by-two, complementing
operation.
Successively connecting the set output of one stage to the complement input of
another stage (Figure A-43) results in frequency division by factors of 4, 8, 16, 32 or 64.
6
In this configuration, the PAC has a capacity as a counter of 0 through 2
- 1, a total of
64 states.
A-71
Advertisement
Table of Contents
