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in the TYDRO flip-flop, a condition necessary to complete the loading and transfer of one
teletype character. ) After the generation of the first shift pulse, notice that the timing
follows the pattern just described.
The only thing that differs is that each new data bit
generated (a total of eight for each character) is entered into TYDR8 and the previously
entered data bits are propagated down the buffer register, with the lower order stages
copying the next highest order stage.
After the ninth shift pulse, the space has been propagated through the buffer register
and stored in TYDRO.
The change in the state of TYDRO resets the TYCFA flip-flop,
in conjunction with TYOUT- and TYKlP+, inhibiting the generation of additional
s~ift
pulses.
Further, with both TYCFA and TYCFB reset, the TYSTP flip-flop is set on the trailing
edge of TYK2P+ (LBD 340 C5 and E5).
Concurrent with the generation of the ninth shift
pulse is the forcing of TYDTA to a mark condition.
Since the TYSTP flip-flop is set,
conditions are present at the input of the busy flip-flop to reset it at the trailing edge of
TYSTP+, which stops the clock and sets the ready flip-flop TYRDY.
The CPU detects that the ASR has information to transfer in one of two ways:
either
by SKS '0004 or SKS '0204 (Skip if ASR is Ready in ASCII Mode, or Skip if ASR is Ready
in Binary Mode); or by program interrupt on the PILOO- line if mask flip-flop TYMSK is
set (LBD 342).
As a result, either of four INA instructions is given INA '0004, '1004,
1
0204, or '1204) and the data is strobed into the CPU.
The CPU signals the ASR that it
will accept the data by generating signal RRLIN-.
RRLIN+ and TYADX+ generate signal TYRRL- which resets the ready flip-flop
(LBD 342).
TYADX- is used to strobe the contents of the buffer register <?nto the input
bus (LBD 341).
The interface is now ready for the next character from the ASR.
Output Mode
The output mode discussion is entered with the generation of an OTA.
This is done
to avoid complicating the discussion with events (a dummy cycle} that occur prior to the gen-
eration of the OTA.
The dummy cycle is discussed in later text.
Assume that an OTA '0004 is issued.
A function of this instruction is to generate
signal RRLIN-.
RR LIN-,
in conjunction with TYADX+ generates TYRRL- and in conjunction
with TYADX+ and TYOUT+ generates TYOTP-. TYRRL- resets the ready flip-flop
(TYRDY, LBD 342}. (See Figure 2-32 for timing diagram.}
TYOTP- performs several functions.
First, it resets TYDRO in the buffer register
(LBD 341).
When TYDRO is reset, the conditions for generating TYRCF- are no longer
present to hold TYCFA reset.
Then, it generates TYTCP- which sets the busy flip-flop
(TYBSY, LBD 340).
TYOTP+ is used to load the data from the output bus into the buffer
register (LBD 342).
The trailing edge of TYOTP+ sets the TYCBC flip-flop, making
TYDTA+ true.
With both TYDRO and TYCFB reset, conditions are present to set TYCFA with the
first TYKlP+ (see TYCAL, LBD 340).
Further, note that the inputs to signal driver/receiver
L lA 16 are both ZERO, causing a space to be sent to ASR ( TYSIG- drops to less than 3 ma,
the space condition}.
2-50
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